| Message ID | 20231220004638.2463643-5-cristian.ciocaltea@collabora.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable networking support for StarFive JH7100 SoC | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
Cristian Ciocaltea wrote: > The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting > RGMII-ID which doesn't require any particular setup, other than defining > a reset gpio, as opposed to VisionFive V1 for which the RX internal > delay had to be adjusted. > > Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> > --- > .../boot/dts/starfive/jh7100-beaglev-starlight.dts | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts > index 7cda3a89020a..b79426935bfd 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts > +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts > @@ -11,3 +11,14 @@ / { > model = "BeagleV Starlight Beta"; > compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; > }; > + > +&mdio { > + phy: ethernet-phy@7 { > + reg = <7>; > + reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; > + }; > +}; > + > +&gmac { > + phy-handle = <&phy>; > +}; ..and here.
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts index 7cda3a89020a..b79426935bfd 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts @@ -11,3 +11,14 @@ / { model = "BeagleV Starlight Beta"; compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; }; + +&mdio { + phy: ethernet-phy@7 { + reg = <7>; + reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + }; +}; + +&gmac { + phy-handle = <&phy>; +};