| Message ID | 20231220-sa8295p-gpu-v1-6-d8cdf2257f97@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: sa8295p: Enable GPU | expand |
On Thu, 21 Dec 2023 at 05:52, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > From: Bjorn Andersson <andersson@kernel.org> > > The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the > VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the > bus. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 40 ++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > index fd253942e5e5..e16406c9c19d 100644 > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > @@ -266,6 +266,26 @@ &dispcc1 { > status = "okay"; > }; > > +&i2c12 { > + pinctrl-names = "default"; > + pinctrl-0 = <&qup1_i2c4_state>; > + > + status = "okay"; > + > + vdd_gfx: regulator@39 { > + compatible = "maxim,max20411"; > + reg = <0x39>; > + > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <968750>; > + > + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&max20411_en>; > + }; > +}; > + > &mdss0 { > status = "okay"; > }; > @@ -476,6 +496,10 @@ &pcie4_phy { > status = "okay"; > }; > > +&qup1 { > + status = "okay"; > +}; > + > &qup2 { > status = "okay"; > }; > @@ -728,4 +752,20 @@ wake-n-pins { > bias-pull-up; > }; > }; > + > + qup1_i2c4_state: qup1-i2c4-state { > + pins = "gpio0", "gpio1"; > + function = "qup12"; > + > + drive-strength = <2>; > + bias-pull-up; > + }; > +}; > + > +&pmm8540a_gpios { I think pmm8540a_gpios comes before tlmm in the dictionary order. Other than that LGTM > + max20411_en: max20411-en-state { > + pins = "gpio2"; > + function = "normal"; > + output-enable; > + }; > };
On 21.12.2023 04:50, Bjorn Andersson wrote: > From: Bjorn Andersson <andersson@kernel.org> > > The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the > VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the > bus. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 40 ++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > index fd253942e5e5..e16406c9c19d 100644 > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > @@ -266,6 +266,26 @@ &dispcc1 { > status = "okay"; > }; > > +&i2c12 { > + pinctrl-names = "default"; > + pinctrl-0 = <&qup1_i2c4_state>; property-n property-names (same below) > + > + status = "okay"; > + > + vdd_gfx: regulator@39 { > + compatible = "maxim,max20411"; > + reg = <0x39>; > + > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <968750>; Is this ever going to be scaled? I suppose you could add some OPP code to drm/msm and use opp-microvolts.. Or lock this down at min=max Konrad
On Thu, Dec 21, 2023 at 01:51:58PM +0100, Konrad Dybcio wrote: > On 21.12.2023 04:50, Bjorn Andersson wrote: > > From: Bjorn Andersson <andersson@kernel.org> > > > > The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the > > VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the > > bus. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 40 ++++++++++++++++++++++++++++++++ > > 1 file changed, 40 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > > index fd253942e5e5..e16406c9c19d 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > > @@ -266,6 +266,26 @@ &dispcc1 { > > status = "okay"; > > }; > > > > +&i2c12 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&qup1_i2c4_state>; > property-n > property-names > > (same below) > > + > > + status = "okay"; > > + > > + vdd_gfx: regulator@39 { > > + compatible = "maxim,max20411"; > > + reg = <0x39>; > > + > > + regulator-min-microvolt = <800000>; > > + regulator-max-microvolt = <968750>; > Is this ever going to be scaled? I suppose you could add some OPP code to > drm/msm and use opp-microvolts.. Or lock this down at min=max > Downstream leave it at 0.8V, so let's lock it down for now. Regards, Bjorn > Konrad
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..e16406c9c19d 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -266,6 +266,26 @@ &dispcc1 { status = "okay"; }; +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&qup1_i2c4_state>; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <968750>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&max20411_en>; + }; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +496,10 @@ &pcie4_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -728,4 +752,20 @@ wake-n-pins { bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + + drive-strength = <2>; + bias-pull-up; + }; +}; + +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; };