| Message ID | 20231222063648.11193-2-quic_kriskura@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Refine USB interrupt vectors on Qualcomm platforms | expand |
On 22/12/2023 07:36, Krishna Kurapati wrote: > The high speed related interrupts present on QC targets are as follows: > > > interrupt-names: > - minItems: 1 > - maxItems: 4 > + minItems: 2 > + maxItems: 5 > > qcom,select-utmi-as-pipe-clk: > description: > @@ -361,60 +378,21 @@ allOf: > compatible: > contains: > enum: > - - qcom,ipq4019-dwc3 Why do you remove it, without adding it somewhere else. Nothing in the commit msg explains it. > + - qcom,ipq5018-dwc3 > - qcom,ipq6018-dwc3 > - - qcom,ipq8064-dwc3 > - qcom,ipq8074-dwc3 > - - qcom,msm8994-dwc3 > - - qcom,qcs404-dwc3 > - - qcom,sc7180-dwc3 > - - qcom,sdm670-dwc3 > - - qcom,sdm845-dwc3 > - - qcom,sdx55-dwc3 > - - qcom,sdx65-dwc3 > - - qcom,sdx75-dwc3 > - - qcom,sm4250-dwc3 > - - qcom,sm6350-dwc3 > - - qcom,sm8150-dwc3 > - - qcom,sm8250-dwc3 > - - qcom,sm8350-dwc3 > - - qcom,sm8450-dwc3 > - - qcom,sm8550-dwc3 > - - qcom,sm8650-dwc3 > - then: > - properties: > - interrupts: > - items: > - - description: The interrupt that is asserted > - when a wakeup event is received on USB2 bus. > - - description: The interrupt that is asserted > - when a wakeup event is received on USB3 bus. > - - description: Wakeup event on DM line. > - - description: Wakeup event on DP line. > - interrupt-names: > - items: > - - const: hs_phy_irq > - - const: ss_phy_irq > - - const: dm_hs_phy_irq > - - const: dp_hs_phy_irq > - > - - if: > - properties: > - compatible: > - contains: > - enum: > - qcom,msm8953-dwc3 > - - qcom,msm8996-dwc3 > - qcom,msm8998-dwc3 > - - qcom,sm6115-dwc3 > - - qcom,sm6125-dwc3 > + - qcom,qcm2290-dwc3 > then: > properties: > interrupts: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > interrupt-names: > items: > - - const: hs_phy_irq > + - const: pwr_event > + - const: qusb2_phy > - const: ss_phy_irq > > - if: > @@ -422,37 +400,21 @@ allOf: > compatible: > contains: > enum: > - - qcom,ipq5018-dwc3 > - - qcom,ipq5332-dwc3 > + - qcom,msm8996-dwc3 > + - qcom,qcs404-dwc3 > - qcom,sdm660-dwc3 > - then: > - properties: > - interrupts: > - minItems: 1 > - maxItems: 2 > - interrupt-names: > - minItems: 1 > - items: > - - const: hs_phy_irq > - - const: ss_phy_irq > - > - - if: > - properties: > - compatible: > - contains: > - enum: > - - qcom,sc7280-dwc3 > + - qcom,sm6115-dwc3 > + - qcom,sm6125-dwc3 > then: > properties: > interrupts: > minItems: 3 > maxItems: 4 > interrupt-names: > - minItems: 3 > items: > + - const: pwr_event > - const: hs_phy_irq > - - const: dp_hs_phy_irq > - - const: dm_hs_phy_irq > + - const: qusb2_phy Why qusb2_phy is after hs_phy_irq? In the earlier if:then: it is the second one. > - const: ss_phy_irq > > - if: > @@ -460,11 +422,13 @@ allOf: > compatible: > contains: > enum: > + - qcom,ipq5332-dwc3 > - qcom,sc8280xp-dwc3 > - qcom,x1e80100-dwc3 > then: > properties: > interrupts: > + minItems: 3 Hm, why? This commit is unmanageable. Your commit msg is already huge but still does not explain this. Are you sure you are fixing only one logical thing per patch? Does not look like. Best regards, Krzysztof
On 12/25/2023 6:35 PM, Krzysztof Kozlowski wrote: > On 22/12/2023 07:36, Krishna Kurapati wrote: >> The high speed related interrupts present on QC targets are as follows: >> > > >> >> interrupt-names: >> - minItems: 1 >> - maxItems: 4 >> + minItems: 2 >> + maxItems: 5 >> >> qcom,select-utmi-as-pipe-clk: >> description: >> @@ -361,60 +378,21 @@ allOf: >> compatible: >> contains: >> enum: >> - - qcom,ipq4019-dwc3 > > Why do you remove it, without adding it somewhere else. Nothing in the > commit msg explains it. > Apologies, Will check and add it back. >> + - qcom,ipq5018-dwc3 >> - qcom,ipq6018-dwc3 >> - - qcom,ipq8064-dwc3 >> - qcom,ipq8074-dwc3 >> - - qcom,msm8994-dwc3 >> - - qcom,qcs404-dwc3 >> - - qcom,sc7180-dwc3 >> - - qcom,sdm670-dwc3 >> - - qcom,sdm845-dwc3 >> - - qcom,sdx55-dwc3 >> - - qcom,sdx65-dwc3 >> - - qcom,sdx75-dwc3 >> - - qcom,sm4250-dwc3 >> - - qcom,sm6350-dwc3 >> - - qcom,sm8150-dwc3 >> - - qcom,sm8250-dwc3 >> - - qcom,sm8350-dwc3 >> - - qcom,sm8450-dwc3 >> - - qcom,sm8550-dwc3 >> - - qcom,sm8650-dwc3 >> - then: >> - properties: >> - interrupts: >> - items: >> - - description: The interrupt that is asserted >> - when a wakeup event is received on USB2 bus. >> - - description: The interrupt that is asserted >> - when a wakeup event is received on USB3 bus. >> - - description: Wakeup event on DM line. >> - - description: Wakeup event on DP line. >> - interrupt-names: >> - items: >> - - const: hs_phy_irq >> - - const: ss_phy_irq >> - - const: dm_hs_phy_irq >> - - const: dp_hs_phy_irq >> - >> - - if: >> - properties: >> - compatible: >> - contains: >> - enum: >> - qcom,msm8953-dwc3 >> - - qcom,msm8996-dwc3 >> - qcom,msm8998-dwc3 >> - - qcom,sm6115-dwc3 >> - - qcom,sm6125-dwc3 >> + - qcom,qcm2290-dwc3 >> then: >> properties: >> interrupts: >> - maxItems: 2 >> + minItems: 2 >> + maxItems: 3 >> interrupt-names: >> items: >> - - const: hs_phy_irq >> + - const: pwr_event >> + - const: qusb2_phy >> - const: ss_phy_irq >> >> - if: >> @@ -422,37 +400,21 @@ allOf: >> compatible: >> contains: >> enum: >> - - qcom,ipq5018-dwc3 >> - - qcom,ipq5332-dwc3 >> + - qcom,msm8996-dwc3 >> + - qcom,qcs404-dwc3 >> - qcom,sdm660-dwc3 >> - then: >> - properties: >> - interrupts: >> - minItems: 1 >> - maxItems: 2 >> - interrupt-names: >> - minItems: 1 >> - items: >> - - const: hs_phy_irq >> - - const: ss_phy_irq >> - >> - - if: >> - properties: >> - compatible: >> - contains: >> - enum: >> - - qcom,sc7280-dwc3 >> + - qcom,sm6115-dwc3 >> + - qcom,sm6125-dwc3 >> then: >> properties: >> interrupts: >> minItems: 3 >> maxItems: 4 >> interrupt-names: >> - minItems: 3 >> items: >> + - const: pwr_event >> - const: hs_phy_irq >> - - const: dp_hs_phy_irq >> - - const: dm_hs_phy_irq >> + - const: qusb2_phy > > Why qusb2_phy is after hs_phy_irq? In the earlier if:then: it is the > second one. > In v3 as well, the hs_phy_irq is before qusb2_phy interrupt: https://lore.kernel.org/all/20231211121124.4194-2-quic_kriskura@quicinc.com/ > >> - const: ss_phy_irq >> >> - if: >> @@ -460,11 +422,13 @@ allOf: >> compatible: >> contains: >> enum: >> + - qcom,ipq5332-dwc3 >> - qcom,sc8280xp-dwc3 >> - qcom,x1e80100-dwc3 >> then: >> properties: >> interrupts: >> + minItems: 3 > > Hm, why? This commit is unmanageable. Your commit msg is already huge > but still does not explain this. Are you sure you are fixing only one > logical thing per patch? Does not look like. > This is reordering the targets based on interrupts they have. I put it in one commit because splitting this into multiple patches breaks one thing or other. Also once I am defining permutations, I have to group targets into these combinations in the same patch. I know this is a big commit but it solves the interrupt cleanup and defines a way for future targets. Regards, Krishna,
On 26/12/2023 06:37, Krishna Kurapati PSSNV wrote: > > > On 12/25/2023 6:35 PM, Krzysztof Kozlowski wrote: >> On 22/12/2023 07:36, Krishna Kurapati wrote: >>> The high speed related interrupts present on QC targets are as follows: >>> >> >> >>> >>> interrupt-names: >>> - minItems: 1 >>> - maxItems: 4 >>> + minItems: 2 >>> + maxItems: 5 >>> >>> qcom,select-utmi-as-pipe-clk: >>> description: >>> @@ -361,60 +378,21 @@ allOf: >>> compatible: >>> contains: >>> enum: >>> - - qcom,ipq4019-dwc3 >> >> Why do you remove it, without adding it somewhere else. Nothing in the >> commit msg explains it. >> > > Apologies, Will check and add it back. Please check your patch for other entries. I just took first compatible which turns out to be gone. I did not check the reset and I don't want to keep checking. ... >>> - then: >>> - properties: >>> - interrupts: >>> - minItems: 1 >>> - maxItems: 2 >>> - interrupt-names: >>> - minItems: 1 >>> - items: >>> - - const: hs_phy_irq >>> - - const: ss_phy_irq >>> - >>> - - if: >>> - properties: >>> - compatible: >>> - contains: >>> - enum: >>> - - qcom,sc7280-dwc3 >>> + - qcom,sm6115-dwc3 >>> + - qcom,sm6125-dwc3 >>> then: >>> properties: >>> interrupts: >>> minItems: 3 >>> maxItems: 4 >>> interrupt-names: >>> - minItems: 3 >>> items: >>> + - const: pwr_event >>> - const: hs_phy_irq >>> - - const: dp_hs_phy_irq >>> - - const: dm_hs_phy_irq >>> + - const: qusb2_phy >> >> Why qusb2_phy is after hs_phy_irq? In the earlier if:then: it is the >> second one. >> > > In v3 as well, the hs_phy_irq is before qusb2_phy interrupt: > https://lore.kernel.org/all/20231211121124.4194-2-quic_kriskura@quicinc.com/ ? How v3 matters? > >> >>> - const: ss_phy_irq >>> >>> - if: >>> @@ -460,11 +422,13 @@ allOf: >>> compatible: >>> contains: >>> enum: >>> + - qcom,ipq5332-dwc3 >>> - qcom,sc8280xp-dwc3 >>> - qcom,x1e80100-dwc3 >>> then: >>> properties: >>> interrupts: >>> + minItems: 3 >> >> Hm, why? This commit is unmanageable. Your commit msg is already huge >> but still does not explain this. Are you sure you are fixing only one >> logical thing per patch? Does not look like. >> > > This is reordering the targets based on interrupts they have. I put it > in one commit because splitting this into multiple patches breaks one > thing or other. Also once I am defining permutations, I have to group > targets into these combinations in the same patch. I know this is a big > commit but it solves the interrupt cleanup and defines a way for future > targets. This does not answer why, you sc8280xp and x1e80100 not get one optional interrupt. I asked "why" you are doing this change. Why do you need it? What is the rationale? Then I grunted about unmanageable commit, because all my troubles to review it are the effect of it: it is very difficult to read. It is also difficult for you, because you keep making here mistakes. So if you cannot write this commit properly and I cannot review it, then it is way over-complicated, don't you think? But this is still second problem here, don't ignore the fist - "why?" Best regards, Krzysztof
On 12/26/2023 3:03 PM, Krzysztof Kozlowski wrote: > On 26/12/2023 06:37, Krishna Kurapati PSSNV wrote: >> >> >> On 12/25/2023 6:35 PM, Krzysztof Kozlowski wrote: >>> On 22/12/2023 07:36, Krishna Kurapati wrote: >>>> The high speed related interrupts present on QC targets are as follows: >>>> >>> >>> >>>> >>>> interrupt-names: >>>> - minItems: 1 >>>> - maxItems: 4 >>>> + minItems: 2 >>>> + maxItems: 5 >>>> >>>> qcom,select-utmi-as-pipe-clk: >>>> description: >>>> @@ -361,60 +378,21 @@ allOf: >>>> compatible: >>>> contains: >>>> enum: >>>> - - qcom,ipq4019-dwc3 >>> >>> Why do you remove it, without adding it somewhere else. Nothing in the >>> commit msg explains it. >>> >> >> Apologies, Will check and add it back. > > Please check your patch for other entries. I just took first compatible > which turns out to be gone. I did not check the reset and I don't want > to keep checking. > > ... > >>>> - then: >>>> - properties: >>>> - interrupts: >>>> - minItems: 1 >>>> - maxItems: 2 >>>> - interrupt-names: >>>> - minItems: 1 >>>> - items: >>>> - - const: hs_phy_irq >>>> - - const: ss_phy_irq >>>> - >>>> - - if: >>>> - properties: >>>> - compatible: >>>> - contains: >>>> - enum: >>>> - - qcom,sc7280-dwc3 >>>> + - qcom,sm6115-dwc3 >>>> + - qcom,sm6125-dwc3 >>>> then: >>>> properties: >>>> interrupts: >>>> minItems: 3 >>>> maxItems: 4 >>>> interrupt-names: >>>> - minItems: 3 >>>> items: >>>> + - const: pwr_event >>>> - const: hs_phy_irq >>>> - - const: dp_hs_phy_irq >>>> - - const: dm_hs_phy_irq >>>> + - const: qusb2_phy >>> >>> Why qusb2_phy is after hs_phy_irq? In the earlier if:then: it is the >>> second one. >>> >> >> In v3 as well, the hs_phy_irq is before qusb2_phy interrupt: >> https://lore.kernel.org/all/20231211121124.4194-2-quic_kriskura@quicinc.com/ > > ? How v3 matters? > >> >>> >>>> - const: ss_phy_irq >>>> >>>> - if: >>>> @@ -460,11 +422,13 @@ allOf: >>>> compatible: >>>> contains: >>>> enum: >>>> + - qcom,ipq5332-dwc3 >>>> - qcom,sc8280xp-dwc3 >>>> - qcom,x1e80100-dwc3 >>>> then: >>>> properties: >>>> interrupts: >>>> + minItems: 3 >>> >>> Hm, why? This commit is unmanageable. Your commit msg is already huge >>> but still does not explain this. Are you sure you are fixing only one >>> logical thing per patch? Does not look like. >>> >> >> This is reordering the targets based on interrupts they have. I put it >> in one commit because splitting this into multiple patches breaks one >> thing or other. Also once I am defining permutations, I have to group >> targets into these combinations in the same patch. I know this is a big >> commit but it solves the interrupt cleanup and defines a way for future >> targets. > > > This does not answer why, you sc8280xp and x1e80100 not get one optional > interrupt. I asked "why" you are doing this change. Why do you need it? > What is the rationale? > > Then I grunted about unmanageable commit, because all my troubles to > review it are the effect of it: it is very difficult to read. It is also > difficult for you, because you keep making here mistakes. So if you > cannot write this commit properly and I cannot review it, then it is way > over-complicated, don't you think? But this is still second problem > here, don't ignore the fist - "why?" HI Krzysztof, Thanks for the review. To answer the question, "why ?" : The interrupts have been mis-interpreted on many platforms or many interrupts are missing. Now, if I am adding the missing interrupts, I need to segregate targets also into respective buckets in the same patch and that is what making this patch a little complicated. Is it possible / acceptable to split this into two patches if this is the case. Can you help with suggestions from your end ? Or may be I am understanding your question wrong ?
On 26/12/2023 11:03, Krishna Kurapati PSSNV wrote: >>>>> - if: >>>>> @@ -460,11 +422,13 @@ allOf: >>>>> compatible: >>>>> contains: >>>>> enum: >>>>> + - qcom,ipq5332-dwc3 >>>>> - qcom,sc8280xp-dwc3 >>>>> - qcom,x1e80100-dwc3 >>>>> then: >>>>> properties: >>>>> interrupts: >>>>> + minItems: 3 >>>> >>>> Hm, why? This commit is unmanageable. Your commit msg is already huge >>>> but still does not explain this. Are you sure you are fixing only one >>>> logical thing per patch? Does not look like. >>>> >>> >>> This is reordering the targets based on interrupts they have. I put it >>> in one commit because splitting this into multiple patches breaks one >>> thing or other. Also once I am defining permutations, I have to group >>> targets into these combinations in the same patch. I know this is a big >>> commit but it solves the interrupt cleanup and defines a way for future >>> targets. >> >> >> This does not answer why, you sc8280xp and x1e80100 not get one optional >> interrupt. I asked "why" you are doing this change. Why do you need it? >> What is the rationale? >> >> Then I grunted about unmanageable commit, because all my troubles to >> review it are the effect of it: it is very difficult to read. It is also >> difficult for you, because you keep making here mistakes. So if you >> cannot write this commit properly and I cannot review it, then it is way >> over-complicated, don't you think? But this is still second problem >> here, don't ignore the fist - "why?" > > HI Krzysztof, > > Thanks for the review. > To answer the question, > > "why ?" : The interrupts have been mis-interpreted on many platforms or > many interrupts are missing. I asked about these two specific platforms. Please explain these changes. Above is so generic that tells me nothing. > > Now, if I am adding the missing interrupts, I need to segregate targets > also into respective buckets in the same patch and that is what making > this patch a little complicated. Is it possible / acceptable to split > this into two patches if this is the case. Can you help with suggestions > from your end ? Or may be I am understanding your question wrong ?
On 12/26/2023 5:52 PM, Krzysztof Kozlowski wrote: >>> >>> This does not answer why, you sc8280xp and x1e80100 not get one optional >>> interrupt. I asked "why" you are doing this change. Why do you need it? >>> What is the rationale? >>> >>> Then I grunted about unmanageable commit, because all my troubles to >>> review it are the effect of it: it is very difficult to read. It is also >>> difficult for you, because you keep making here mistakes. So if you >>> cannot write this commit properly and I cannot review it, then it is way >>> over-complicated, don't you think? But this is still second problem >>> here, don't ignore the fist - "why?" >> >> HI Krzysztof, >> >> Thanks for the review. >> To answer the question, >> >> "why ?" : The interrupts have been mis-interpreted on many platforms or >> many interrupts are missing. > > I asked about these two specific platforms. Please explain these > changes. Above is so generic that tells me nothing. > Is the question, "Why do x1e80100 and sc8280 don't have hs_phy_irq ?" If so, I checked the SC8280 HW specifics and I see one small error. The name was printed wrong. I got it from another source. Will move sc8280 to list having 5 interrupts. As per x1e80100, I wasn't able to get my hands on the hw specifics and I followed the following link by Abel Vesa: https://lore.kernel.org/r/20231214-x1e80100-usb-v1-1-c22be5c0109e@linaro.org As per the above patch, x1e80100 had only 4 interrupts. For ipq5332, it has no hs_phy_irq and so I kept it under this section. >> >> Now, if I am adding the missing interrupts, I need to segregate targets >> also into respective buckets in the same patch and that is what making >> this patch a little complicated. Is it possible / acceptable to split >> this into two patches if this is the case. Can you help with suggestions >> from your end ? Or may be I am understanding your question wrong ?
On 26/12/2023 16:03, Krishna Kurapati PSSNV wrote: > > > On 12/26/2023 5:52 PM, Krzysztof Kozlowski wrote: > >>>> >>>> This does not answer why, you sc8280xp and x1e80100 not get one optional >>>> interrupt. I asked "why" you are doing this change. Why do you need it? >>>> What is the rationale? >>>> >>>> Then I grunted about unmanageable commit, because all my troubles to >>>> review it are the effect of it: it is very difficult to read. It is also >>>> difficult for you, because you keep making here mistakes. So if you >>>> cannot write this commit properly and I cannot review it, then it is way >>>> over-complicated, don't you think? But this is still second problem >>>> here, don't ignore the fist - "why?" >>> >>> HI Krzysztof, >>> >>> Thanks for the review. >>> To answer the question, >>> >>> "why ?" : The interrupts have been mis-interpreted on many platforms or >>> many interrupts are missing. >> >> I asked about these two specific platforms. Please explain these >> changes. Above is so generic that tells me nothing. >> > > Is the question, "Why do x1e80100 and sc8280 don't have hs_phy_irq ?" No, not entirely, the question was why these have flexible number of IRQs (last one optional)? > If so, I checked the SC8280 HW specifics and I see one small error. The > name was printed wrong. I got it from another source. Will move sc8280 > to list having 5 interrupts. As per x1e80100, I wasn't able to get my > hands on the hw specifics and I followed the following link by Abel Vesa: > > https://lore.kernel.org/r/20231214-x1e80100-usb-v1-1-c22be5c0109e@linaro.org > > As per the above patch, x1e80100 had only 4 interrupts. Hm, ok, you say "4" but your patch says "minItems: 3". 3 != 4. > For ipq5332, it has no hs_phy_irq and so I kept it under this section. > >>> >>> Now, if I am adding the missing interrupts, I need to segregate targets >>> also into respective buckets in the same patch and that is what making >>> this patch a little complicated. Is it possible / acceptable to split >>> this into two patches if this is the case. Can you help with suggestions >>> from your end ? Or may be I am understanding your question wrong ?
On 12/27/2023 12:34 AM, Krzysztof Kozlowski wrote: > On 26/12/2023 16:03, Krishna Kurapati PSSNV wrote: >> >> >> On 12/26/2023 5:52 PM, Krzysztof Kozlowski wrote: >> >>>>> >>>>> This does not answer why, you sc8280xp and x1e80100 not get one optional >>>>> interrupt. I asked "why" you are doing this change. Why do you need it? >>>>> What is the rationale? >>>>> >>>>> Then I grunted about unmanageable commit, because all my troubles to >>>>> review it are the effect of it: it is very difficult to read. It is also >>>>> difficult for you, because you keep making here mistakes. So if you >>>>> cannot write this commit properly and I cannot review it, then it is way >>>>> over-complicated, don't you think? But this is still second problem >>>>> here, don't ignore the fist - "why?" >>>> >>>> HI Krzysztof, >>>> >>>> Thanks for the review. >>>> To answer the question, >>>> >>>> "why ?" : The interrupts have been mis-interpreted on many platforms or >>>> many interrupts are missing. >>> >>> I asked about these two specific platforms. Please explain these >>> changes. Above is so generic that tells me nothing. >>> >> >> Is the question, "Why do x1e80100 and sc8280 don't have hs_phy_irq ?" > > No, not entirely, the question was why these have flexible number of > IRQs (last one optional)? > > >> If so, I checked the SC8280 HW specifics and I see one small error. The >> name was printed wrong. I got it from another source. Will move sc8280 >> to list having 5 interrupts. As per x1e80100, I wasn't able to get my >> hands on the hw specifics and I followed the following link by Abel Vesa: >> >> https://lore.kernel.org/r/20231214-x1e80100-usb-v1-1-c22be5c0109e@linaro.org >> >> As per the above patch, x1e80100 had only 4 interrupts. > > Hm, ok, you say "4" but your patch says "minItems: 3". 3 != 4. > Actually, you are right. We don't need the max/min items as we are sure that the targets mentioned under this have 4 interrupts definitively. But the optional interrupt was put in just in case any target comes in that has no ss_phy and no hs_phy and has only the other 3 interrupts. Since those targets are not present currently, I will remove the max/min items from this. Thanks for the catch. Sorry for bothering you with a couple of mails because I didn't understand the question you were trying to ask. Regards, Krishna,
>>>> interrupt-names: >>>> - minItems: 3 >>>> items: >>>> + - const: pwr_event >>>> - const: hs_phy_irq >>>> - - const: dp_hs_phy_irq >>>> - - const: dm_hs_phy_irq >>>> + - const: qusb2_phy >>> >>> Why qusb2_phy is after hs_phy_irq? In the earlier if:then: it is the >>> second one. >>> >> >> In v3 as well, the hs_phy_irq is before qusb2_phy interrupt: >> https://lore.kernel.org/all/20231211121124.4194-2-quic_kriskura@quicinc.com/ > > ? How v3 matters? > I was thinking whether I modified the order between v3 and v5 and didn't mention in change log and hence I compared with v3. Thanks for the catch. I made qusb2_phy the second one in the list and pushed v6: https://lore.kernel.org/all/20231227091951.685-1-quic_kriskura@quicinc.com/ Can you help provide you review on v6 as well. Regards, Krishna,
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 473c4bfaf8a2..1964b5ad83b7 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -99,12 +99,29 @@ properties: - const: apps-usb interrupts: - minItems: 1 - maxItems: 4 + description: | + Different types of interrupts are used based on HS PHY used on target: + - pwr_event: Used for wakeup based on other power events. + - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + hs_phy_irq which is not triggered by default and its + functionality is mutually exclusive to that of + {dp/dm}_hs_phy_irq and qusb2_phy_irq. + - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and + expose only a single IRQ whose behavior can be modified + by the QUSB2PHY_INTR_CTRL register. The required DPSE/ + DMSE configuration is done in QUSB2PHY_INTR_CTRL register + of PHY address space. + - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ + DM pads of the SoC. These are used for wakeup + only on SoCs with non-QUSB2 targets with + exception of SDM670/SDM845/SM6350. + - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. + minItems: 2 + maxItems: 5 interrupt-names: - minItems: 1 - maxItems: 4 + minItems: 2 + maxItems: 5 qcom,select-utmi-as-pipe-clk: description: @@ -361,60 +378,21 @@ allOf: compatible: contains: enum: - - qcom,ipq4019-dwc3 + - qcom,ipq5018-dwc3 - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 - - qcom,msm8994-dwc3 - - qcom,qcs404-dwc3 - - qcom,sc7180-dwc3 - - qcom,sdm670-dwc3 - - qcom,sdm845-dwc3 - - qcom,sdx55-dwc3 - - qcom,sdx65-dwc3 - - qcom,sdx75-dwc3 - - qcom,sm4250-dwc3 - - qcom,sm6350-dwc3 - - qcom,sm8150-dwc3 - - qcom,sm8250-dwc3 - - qcom,sm8350-dwc3 - - qcom,sm8450-dwc3 - - qcom,sm8550-dwc3 - - qcom,sm8650-dwc3 - then: - properties: - interrupts: - items: - - description: The interrupt that is asserted - when a wakeup event is received on USB2 bus. - - description: The interrupt that is asserted - when a wakeup event is received on USB3 bus. - - description: Wakeup event on DM line. - - description: Wakeup event on DP line. - interrupt-names: - items: - - const: hs_phy_irq - - const: ss_phy_irq - - const: dm_hs_phy_irq - - const: dp_hs_phy_irq - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8953-dwc3 - - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - - qcom,sm6115-dwc3 - - qcom,sm6125-dwc3 + - qcom,qcm2290-dwc3 then: properties: interrupts: - maxItems: 2 + minItems: 2 + maxItems: 3 interrupt-names: items: - - const: hs_phy_irq + - const: pwr_event + - const: qusb2_phy - const: ss_phy_irq - if: @@ -422,37 +400,21 @@ allOf: compatible: contains: enum: - - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 + - qcom,msm8996-dwc3 + - qcom,qcs404-dwc3 - qcom,sdm660-dwc3 - then: - properties: - interrupts: - minItems: 1 - maxItems: 2 - interrupt-names: - minItems: 1 - items: - - const: hs_phy_irq - - const: ss_phy_irq - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7280-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 then: properties: interrupts: minItems: 3 maxItems: 4 interrupt-names: - minItems: 3 items: + - const: pwr_event - const: hs_phy_irq - - const: dp_hs_phy_irq - - const: dm_hs_phy_irq + - const: qusb2_phy - const: ss_phy_irq - if: @@ -460,11 +422,13 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-dwc3 - qcom,sc8280xp-dwc3 - qcom,x1e80100-dwc3 then: properties: interrupts: + minItems: 3 maxItems: 4 interrupt-names: items: @@ -479,15 +443,30 @@ allOf: contains: enum: - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm6375-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 then: properties: interrupts: - minItems: 3 - maxItems: 4 + minItems: 4 + maxItems: 5 interrupt-names: - minItems: 3 items: - const: pwr_event + - const: hs_phy_irq - const: dp_hs_phy_irq - const: dm_hs_phy_irq - const: ss_phy_irq @@ -525,12 +504,13 @@ examples: <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, - <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>;
The high speed related interrupts present on QC targets are as follows: dp/dm irq's These IRQ's directly reflect changes on the DP/DM pads of the SoC. These are used as wakeup interrupts only on SoCs with non-QUSB2 targets with exception of SDM670/SDM845/SM6350. qusb2_phy irq SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL register. The required DPSE/DMSE configuration is done in QUSB2PHY_INTR_CTRL register of phy address space. hs_phy_irq This is completely different from the above two and is present on all targets with exception of a few IPQ ones. The interrupt is not enabled by default and its functionality is mutually exclusive of qusb2_phy on QUSB targets and DP/DM on femto phy targets. The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" when they should have been "qusb2_phy_irq". On Femto phy targets, the "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", neither of which would never be triggered directly are non-functional currently. The implementation tries to clean up this issue by addressing the discrepencies involved and fixing the hs_phy_irq's in respective DT's. Classify SoC's into four groups based on whether qusb2_phy interrupt or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the SoCs have hs_phy_irq present in them or not. The ss_phy_irq is optional interrupt because there are mutliple SoC's which either support only High Speed or there are multiple controllers within same Soc and the secondary controller is High Speed only capable. This breaks ABI on targets running older kernels, but since the interrupt definitions are given wrong on many targets and to establish proper rules for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is necessary. The bindings put pwr_event as the first interrupt and ss_phy as the last. Since all SoCs have the pwr_event (HS) interrupt, but not all controllers have the SS PHY interrupt, this would prevent expressing that the SS PHY is optional by keeping it last in the binding schema and making sure that minItem = maxItems - 1. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 138 ++++++++---------- 1 file changed, 59 insertions(+), 79 deletions(-)