diff mbox series

[2/3] dt-bindings: clock: Update the gcc resets for sm8150

Message ID 20240104-sm8150-dfs-support-v1-2-a5eebfdc1b12@quicinc.com (mailing list archive)
State Changes Requested, archived
Headers show
Series clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 | expand

Commit Message

Satya Priya Kakitapalli Jan. 4, 2024, 2:23 p.m. UTC
Add all the available resets for the global clock controller
on sm8150.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Krzysztof Kozlowski Jan. 4, 2024, 3:43 p.m. UTC | #1
On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
> Add all the available resets for the global clock controller
> on sm8150.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---

Subject:
Everything can be an update. You also miss prefix. Instead:
dt-bindings: clock: qcom,gcc-sm8150: Add Video camcc whatever foobar
reset IDs

Best regards,
Krzysztof
Satya Priya Kakitapalli Jan. 10, 2024, 9:45 a.m. UTC | #2
On 1/4/2024 9:13 PM, Krzysztof Kozlowski wrote:
> On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
>> Add all the available resets for the global clock controller
>> on sm8150.
>>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
> Subject:
> Everything can be an update. You also miss prefix. Instead:
> dt-bindings: clock: qcom,gcc-sm8150: Add Video camcc whatever foobar
> reset IDs


Okay, will update the subject.


> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index dfefd5e8bf6e..921a33f24d33 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -239,6 +239,9 @@ 
 #define GCC_USB30_PRIM_BCR					26
 #define GCC_USB30_SEC_BCR					27
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
+#define GCC_VIDEO_AXIC_CLK_BCR					29
+#define GCC_VIDEO_AXI0_CLK_BCR					30
+#define GCC_VIDEO_AXI1_CLK_BCR					31
 
 /* GCC GDSCRs */
 #define PCIE_0_GDSC						0