| Message ID | 20240103132838.1501801-1-jiri@resnulli.us (mailing list archive) |
|---|---|
| Headers | show |
| Series | dpll: expose fractional frequency offset value to user | expand |
On Wed, 3 Jan 2024 14:28:35 +0100 Jiri Pirko wrote: > From: Jiri Pirko <jiri@nvidia.com> > > Allow to expose pin fractional frequency offset value over new DPLL > generic netlink attribute. Add an op to get the value from the driver. > Implement this new op in mlx5 driver. Arkadiusz, Vadim, acks?
On 03/01/2024 13:28, Jiri Pirko wrote: > From: Jiri Pirko <jiri@nvidia.com> > > Allow to expose pin fractional frequency offset value over new DPLL > generic netlink attribute. Add an op to get the value from the driver. > Implement this new op in mlx5 driver. > > Jiri Pirko (3): > dpll: expose fractional frequency offset value to user > net/mlx5: DPLL, Use struct to get values from > mlx5_dpll_synce_status_get() > net/mlx5: DPLL, Implement fractional frequency offset get pin op > > Documentation/netlink/specs/dpll.yaml | 11 +++ > drivers/dpll/dpll_netlink.c | 24 +++++ > .../net/ethernet/mellanox/mlx5/core/dpll.c | 94 ++++++++++++------- > include/linux/dpll.h | 3 + > include/uapi/linux/dpll.h | 1 + > 5 files changed, 98 insertions(+), 35 deletions(-) > Interesting attribute, it's good that hardware can expose this info. Did you think about building some monitoring/alerts based on it? For the series (I'm not sure if it's enough for mlx5, but the refactoring looks nice): Acked-By: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>From: Jiri Pirko <jiri@resnulli.us> >Sent: Wednesday, January 3, 2024 2:29 PM > >From: Jiri Pirko <jiri@nvidia.com> > >Allow to expose pin fractional frequency offset value over new DPLL generic >netlink attribute. Add an op to get the value from the driver. >Implement this new op in mlx5 driver. > >Jiri Pirko (3): > dpll: expose fractional frequency offset value to user > net/mlx5: DPLL, Use struct to get values from > mlx5_dpll_synce_status_get() > net/mlx5: DPLL, Implement fractional frequency offset get pin op > > Documentation/netlink/specs/dpll.yaml | 11 +++ > drivers/dpll/dpll_netlink.c | 24 +++++ > .../net/ethernet/mellanox/mlx5/core/dpll.c | 94 ++++++++++++------- > include/linux/dpll.h | 3 + > include/uapi/linux/dpll.h | 1 + > 5 files changed, 98 insertions(+), 35 deletions(-) > >-- >2.43.0 Sure, LGTM. Acked-By: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Hello: This series was applied to netdev/net-next.git (main) by Jakub Kicinski <kuba@kernel.org>: On Wed, 3 Jan 2024 14:28:35 +0100 you wrote: > From: Jiri Pirko <jiri@nvidia.com> > > Allow to expose pin fractional frequency offset value over new DPLL > generic netlink attribute. Add an op to get the value from the driver. > Implement this new op in mlx5 driver. > > Jiri Pirko (3): > dpll: expose fractional frequency offset value to user > net/mlx5: DPLL, Use struct to get values from > mlx5_dpll_synce_status_get() > net/mlx5: DPLL, Implement fractional frequency offset get pin op > > [...] Here is the summary with links: - [net-next,1/3] dpll: expose fractional frequency offset value to user https://git.kernel.org/netdev/net-next/c/8a6286c1804e - [net-next,2/3] net/mlx5: DPLL, Use struct to get values from mlx5_dpll_synce_status_get() https://git.kernel.org/netdev/net-next/c/e6d86938a40a - [net-next,3/3] net/mlx5: DPLL, Implement fractional frequency offset get pin op https://git.kernel.org/netdev/net-next/c/f035dca34ede You are awesome, thank you!
Fri, Jan 05, 2024 at 12:44:23PM CET, vadim.fedorenko@linux.dev wrote: >On 03/01/2024 13:28, Jiri Pirko wrote: >> From: Jiri Pirko <jiri@nvidia.com> >> >> Allow to expose pin fractional frequency offset value over new DPLL >> generic netlink attribute. Add an op to get the value from the driver. >> Implement this new op in mlx5 driver. >> >> Jiri Pirko (3): >> dpll: expose fractional frequency offset value to user >> net/mlx5: DPLL, Use struct to get values from >> mlx5_dpll_synce_status_get() >> net/mlx5: DPLL, Implement fractional frequency offset get pin op >> >> Documentation/netlink/specs/dpll.yaml | 11 +++ >> drivers/dpll/dpll_netlink.c | 24 +++++ >> .../net/ethernet/mellanox/mlx5/core/dpll.c | 94 ++++++++++++------- >> include/linux/dpll.h | 3 + >> include/uapi/linux/dpll.h | 1 + >> 5 files changed, 98 insertions(+), 35 deletions(-) >> > >Interesting attribute, it's good that hardware can expose this info. > >Did you think about building some monitoring/alerts based on it? The deamon we use internally just exposes this to user mainly for debugging purposes now. Not sure about another plans with this. > >For the series (I'm not sure if it's enough for mlx5, but the >refactoring looks nice): > >Acked-By: Vadim Fedorenko <vadim.fedorenko@linux.dev>
From: Jiri Pirko <jiri@nvidia.com> Allow to expose pin fractional frequency offset value over new DPLL generic netlink attribute. Add an op to get the value from the driver. Implement this new op in mlx5 driver. Jiri Pirko (3): dpll: expose fractional frequency offset value to user net/mlx5: DPLL, Use struct to get values from mlx5_dpll_synce_status_get() net/mlx5: DPLL, Implement fractional frequency offset get pin op Documentation/netlink/specs/dpll.yaml | 11 +++ drivers/dpll/dpll_netlink.c | 24 +++++ .../net/ethernet/mellanox/mlx5/core/dpll.c | 94 ++++++++++++------- include/linux/dpll.h | 3 + include/uapi/linux/dpll.h | 1 + 5 files changed, 98 insertions(+), 35 deletions(-)