[v2,0/2] target/riscv: Add support for 'B' extension

Message

Rob Bradford Jan. 11, 2024, 4:16 p.m. UTC

Add support for the new (fast track) 'B' extension [1] this extension
uses the misa.B bit to indicate that the Zba, Zbb and Zbs extensions are
present.

Since this extension is not yet frozen it is exposed via the 'x-b' cpu
option. The validation logic is based on the new approach taken for the
'G' extension.

The specification handles backward compatability: The misa.B bit may be
set if Zba, Zbb and Zbs are present but in order to not break existing
systems the bit is not required to be set if they are present. As such
even though Zba, Zbb and Zbs default to on in QEMU this extension is not
enabled by default in any cpu.

Cheers,

Rob

[1] - https://github.com/riscv/riscv-b

Changes since V1:
- Rebased on master after latest riscv updates
- All patches have R-B tags
- Array formatting fix to make future diffs clean (Daniel)
- Dropped enabling for max CPU variant as misa.B is reserved until
  spec is at least frozen (Daniel & Drew)

Rob Bradford (2):
  target/riscv: Add infrastructure for 'B' MISA extension
  target/riscv: Add step to validate 'B' extension

 target/riscv/cpu.c         |  5 +++--
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.c | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+), 2 deletions(-)

Comments

Alistair Francis Jan. 12, 2024, 1:22 a.m. UTC | #1

On Fri, Jan 12, 2024 at 2:17 AM Rob Bradford <[e-mail]> wrote:
>
> Add support for the new (fast track) 'B' extension [1] this extension
> uses the misa.B bit to indicate that the Zba, Zbb and Zbs extensions are
> present.
>
> Since this extension is not yet frozen it is exposed via the 'x-b' cpu
> option. The validation logic is based on the new approach taken for the
> 'G' extension.
>
> The specification handles backward compatability: The misa.B bit may be
> set if Zba, Zbb and Zbs are present but in order to not break existing
> systems the bit is not required to be set if they are present. As such
> even though Zba, Zbb and Zbs default to on in QEMU this extension is not
> enabled by default in any cpu.
>
> Cheers,
>
> Rob
>
> [1] - https://github.com/riscv/riscv-b
>
> Changes since V1:
> - Rebased on master after latest riscv updates
> - All patches have R-B tags
> - Array formatting fix to make future diffs clean (Daniel)
> - Dropped enabling for max CPU variant as misa.B is reserved until
>   spec is at least frozen (Daniel & Drew)
>
> Rob Bradford (2):
>   target/riscv: Add infrastructure for 'B' MISA extension
>   target/riscv: Add step to validate 'B' extension

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c         |  5 +++--
>  target/riscv/cpu.h         |  1 +
>  target/riscv/tcg/tcg-cpu.c | 33 +++++++++++++++++++++++++++++++++
>  3 files changed, 37 insertions(+), 2 deletions(-)
>
> --
> 2.43.0
>
>