mbox series

[v3,00/13] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen'

Message ID 20240116205817.344178-1-dbarboza@ventanamicro.com (mailing list archive)
Headers show
Series target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' | expand

Message

Daniel Henrique Barboza Jan. 16, 2024, 8:58 p.m. UTC
Hi,

In this v3 the most significant change is with vext_get_vlmax() from
cpu.h. The logic used in this function is also used in at least two
other places, trans_vrgather_vi() and trans_vrgather_vx(), and we need
to make changes in them to remove 'vlen' occurrences.

Instead, we're adding an extra patch (11) to rework vext_get_vlmax()
arguments to make the function usable in trans_vrgather_v*(). This
rework includes some naming changes in local variables - we're using
'vsew' and 'vlmul' more often to be less ambiguous when reading code. 

Series based on Alistair's riscv-to-apply.next.

Patches missing review: patches 10, 11, 12.

Changes from v3:
- patch 8:
  - changed fractional LMUL comment to show the expansion
- patches 9 and 10: switched places
- patch 10 (former 9):
  - use 'vlen' in vext_get_vlmax() to avoid a negative shift 
- patch 11 (new):
  - change vext_get_vlmax() to use 'vlenb', 'vsew' and 'lmul'
- patch 12 (former 11):
  - use vext_get_vlmax() instead of calculating vlmax manually
- v2 link: https://lore.kernel.org/qemu-riscv/20240115222528.257342-1-dbarboza@ventanamicro.com/


Daniel Henrique Barboza (13):
  target/riscv: add 'vlenb' field in cpu->cfg
  target/riscv/csr.c: use 'vlenb' instead of 'vlen'
  target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
  target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
  target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
  target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
  target/riscv/vector_helper.c: use 'vlenb'
  target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
  target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
  target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
  target/riscv: change vext_get_vlmax() arguments
  trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
  target/riscv/cpu.c: remove cpu->cfg.vlen

 target/riscv/cpu.c                         |  12 +-
 target/riscv/cpu.h                         |  14 +-
 target/riscv/cpu_cfg.h                     |   2 +-
 target/riscv/cpu_helper.c                  |  11 +-
 target/riscv/csr.c                         |   4 +-
 target/riscv/gdbstub.c                     |   6 +-
 target/riscv/insn_trans/trans_rvbf16.c.inc |  12 +-
 target/riscv/insn_trans/trans_rvv.c.inc    | 152 ++++++++++-----------
 target/riscv/insn_trans/trans_rvvk.c.inc   |  16 +--
 target/riscv/tcg/tcg-cpu.c                 |   4 +-
 target/riscv/vector_helper.c               |  43 +++---
 11 files changed, 148 insertions(+), 128 deletions(-)

Comments

Alistair Francis Jan. 22, 2024, 3:39 a.m. UTC | #1
On Wed, Jan 17, 2024 at 7:41 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this v3 the most significant change is with vext_get_vlmax() from
> cpu.h. The logic used in this function is also used in at least two
> other places, trans_vrgather_vi() and trans_vrgather_vx(), and we need
> to make changes in them to remove 'vlen' occurrences.
>
> Instead, we're adding an extra patch (11) to rework vext_get_vlmax()
> arguments to make the function usable in trans_vrgather_v*(). This
> rework includes some naming changes in local variables - we're using
> 'vsew' and 'vlmul' more often to be less ambiguous when reading code.
>
> Series based on Alistair's riscv-to-apply.next.
>
> Patches missing review: patches 10, 11, 12.
>
> Changes from v3:
> - patch 8:
>   - changed fractional LMUL comment to show the expansion
> - patches 9 and 10: switched places
> - patch 10 (former 9):
>   - use 'vlen' in vext_get_vlmax() to avoid a negative shift
> - patch 11 (new):
>   - change vext_get_vlmax() to use 'vlenb', 'vsew' and 'lmul'
> - patch 12 (former 11):
>   - use vext_get_vlmax() instead of calculating vlmax manually
> - v2 link: https://lore.kernel.org/qemu-riscv/20240115222528.257342-1-dbarboza@ventanamicro.com/
>
>
> Daniel Henrique Barboza (13):
>   target/riscv: add 'vlenb' field in cpu->cfg
>   target/riscv/csr.c: use 'vlenb' instead of 'vlen'
>   target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
>   target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
>   target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
>   target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
>   target/riscv/vector_helper.c: use 'vlenb'
>   target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
>   target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
>   target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
>   target/riscv: change vext_get_vlmax() arguments
>   trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
>   target/riscv/cpu.c: remove cpu->cfg.vlen

Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?

Alistair

>
>  target/riscv/cpu.c                         |  12 +-
>  target/riscv/cpu.h                         |  14 +-
>  target/riscv/cpu_cfg.h                     |   2 +-
>  target/riscv/cpu_helper.c                  |  11 +-
>  target/riscv/csr.c                         |   4 +-
>  target/riscv/gdbstub.c                     |   6 +-
>  target/riscv/insn_trans/trans_rvbf16.c.inc |  12 +-
>  target/riscv/insn_trans/trans_rvv.c.inc    | 152 ++++++++++-----------
>  target/riscv/insn_trans/trans_rvvk.c.inc   |  16 +--
>  target/riscv/tcg/tcg-cpu.c                 |   4 +-
>  target/riscv/vector_helper.c               |  43 +++---
>  11 files changed, 148 insertions(+), 128 deletions(-)
>
> --
> 2.43.0
>
>