diff mbox series

[RFC,19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS

Message ID 20240119144024.14289-20-anjo@rev.ng (mailing list archive)
State New, archived
Headers show
Series Compile accel/tcg once (partially) | expand

Commit Message

Anton Johansson Jan. 19, 2024, 2:40 p.m. UTC 
[NOTE: We could also use target_long_bits(), which is introduced later]

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/exec/cpu_ldst.h | 31 ++++++++++++++++---------------
 accel/tcg/cputlb.c      | 34 ++++++++++++++++++++--------------
 2 files changed, 36 insertions(+), 29 deletions(-)

Comments

Richard Henderson Jan. 24, 2024, 1:18 a.m. UTC | #1 
On 1/20/24 00:40, Anton Johansson wrote:
> @@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
>                                  unsigned bits)
>   {
>       TLBFlushRangeData d;
> +    const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;

No, this value isn't initialized at the correct time.
We are out of scope here.


r~
diff mbox series

Patch

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 24fe322d72..553e0119f9 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -340,7 +340,7 @@  static inline void clear_helper_retaddr(void)
 
 #else
 
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
 
 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
                                     MMUAccessType access_type)
@@ -353,20 +353,21 @@  static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
     QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
                       MMU_INST_FETCH * sizeof(uint64_t));
 
-#if TARGET_LONG_BITS == 32
-    /* Use qatomic_read, in case of addr_write; only care about low bits. */
-    const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
-    ptr += HOST_BIG_ENDIAN;
-    return qatomic_read(ptr);
-#else
-    const uint64_t *ptr = &entry->addr_idx[access_type];
-# if TCG_OVERSIZED_GUEST
-    return *ptr;
-# else
-    /* ofs might correspond to .addr_write, so use qatomic_read */
-    return qatomic_read(ptr);
-# endif
-#endif
+    if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+        /* Use qatomic_read, in case of addr_write; only care about low bits. */
+        const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
+        ptr += HOST_BIG_ENDIAN;
+        return qatomic_read(ptr);
+    } else {
+        const uint64_t *ptr = &entry->addr_idx[access_type];
+        if (TCG_TARGET_REG_BITS == 32) {
+            /* Oversized guest */
+            return *ptr;
+        } else {
+            /* ofs might correspond to .addr_write, so use qatomic_read */
+            return qatomic_read(ptr);
+        }
+    }
 }
 
 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 449c86301e..967d5da6d4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -41,7 +41,7 @@ 
 #include "qemu/plugin-memory.h"
 #endif
 #include "tcg/tcg-ldst.h"
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
 
 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
 /* #define DEBUG_TLB */
@@ -815,12 +815,13 @@  void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
                                unsigned bits)
 {
     TLBFlushRangeData d;
+    const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
     /*
      * If all bits are significant, and len is small,
      * this devolves to tlb_flush_page.
      */
-    if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+    if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
         tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
         return;
     }
@@ -858,12 +859,13 @@  void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
 {
     TLBFlushRangeData d;
     CPUState *dst_cpu;
+    const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
     /*
      * If all bits are significant, and len is small,
      * this devolves to tlb_flush_page.
      */
-    if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+    if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
         tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
         return;
     }
@@ -908,12 +910,13 @@  void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
 {
     TLBFlushRangeData d, *p;
     CPUState *dst_cpu;
+    const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
     /*
      * If all bits are significant, and len is small,
      * this devolves to tlb_flush_page.
      */
-    if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+    if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
         tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
         return;
     }
@@ -995,16 +998,19 @@  static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
         addr &= TARGET_PAGE_MASK;
         addr += tlb_entry->addend;
         if ((addr - start) < length) {
-#if TARGET_LONG_BITS == 32
-            uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
-            ptr_write += HOST_BIG_ENDIAN;
-            qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
-#elif TCG_OVERSIZED_GUEST
-            tlb_entry->addr_write |= TLB_NOTDIRTY;
-#else
-            qatomic_set(&tlb_entry->addr_write,
-                        tlb_entry->addr_write | TLB_NOTDIRTY);
-#endif
+            if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+                /* 32-bit */
+                uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
+                ptr_write += HOST_BIG_ENDIAN;
+                qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
+            } else if (TCG_TARGET_REG_BITS == 32) {
+                /* Oversized guest */
+                tlb_entry->addr_write |= TLB_NOTDIRTY;
+            } else {
+                /* 64-bit */
+                qatomic_set(&tlb_entry->addr_write,
+                            tlb_entry->addr_write | TLB_NOTDIRTY);
+            }
         }
     }
 }