diff mbox series

[v2,14/16] arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks

Message ID 20231218120712.16438-15-manivannan.sadhasivam@linaro.org (mailing list archive)
State Not Applicable, archived
Headers show
Series Fix Qcom UFS PHY clocks | expand

Commit Message

Manivannan Sadhasivam Dec. 18, 2023, 12:07 p.m. UTC 
QMP PHY used in SC8280XP requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

Comments

Konrad Dybcio Dec. 20, 2023, 12:35 a.m. UTC | #1 
On 18.12.2023 13:07, Manivannan Sadhasivam wrote:
> QMP PHY used in SC8280XP requires 3 clocks:
> 
> * ref - 19.2MHz reference clock from RPMh
> * ref_aux - Auxiliary reference clock from GCC
> * qref - QREF clock from GCC
> 
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index cad59af7ccef..37344abbe8bf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 {
>  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
>  			reg = <0 0x01d87000 0 0x1000>;
>  
> -			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
> -				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> -			clock-names = "ref", "ref_aux";
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> +				 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
GCC_UFS_REF_CLKREF_CLK

?

Konrad
Manivannan Sadhasivam Dec. 20, 2023, 8:30 a.m. UTC | #2 
On Wed, Dec 20, 2023 at 01:35:27AM +0100, Konrad Dybcio wrote:
> On 18.12.2023 13:07, Manivannan Sadhasivam wrote:
> > QMP PHY used in SC8280XP requires 3 clocks:
> > 
> > * ref - 19.2MHz reference clock from RPMh
> > * ref_aux - Auxiliary reference clock from GCC
> > * qref - QREF clock from GCC
> > 
> > Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------
> >  1 file changed, 12 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index cad59af7ccef..37344abbe8bf 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 {
> >  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
> >  			reg = <0 0x01d87000 0 0x1000>;
> >  
> > -			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
> > -				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> > -			clock-names = "ref", "ref_aux";
> > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > +				 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
> GCC_UFS_REF_CLKREF_CLK

I'm not sure about this CLK. So I kept it as it is until I verify it.

- Mani

> 
> ?
> 
> Konrad
Konrad Dybcio Jan. 3, 2024, 1:50 p.m. UTC | #3 
On 20.12.2023 09:30, Manivannan Sadhasivam wrote:
> On Wed, Dec 20, 2023 at 01:35:27AM +0100, Konrad Dybcio wrote:
>> On 18.12.2023 13:07, Manivannan Sadhasivam wrote:
>>> QMP PHY used in SC8280XP requires 3 clocks:
>>>
>>> * ref - 19.2MHz reference clock from RPMh
>>> * ref_aux - Auxiliary reference clock from GCC
>>> * qref - QREF clock from GCC
>>>
>>> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------
>>>  1 file changed, 12 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> index cad59af7ccef..37344abbe8bf 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 {
>>>  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
>>>  			reg = <0 0x01d87000 0 0x1000>;
>>>  
>>> -			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
>>> -				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>>> -			clock-names = "ref", "ref_aux";
>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>> +				 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
>> GCC_UFS_REF_CLKREF_CLK
> 
> I'm not sure about this CLK. So I kept it as it is until I verify it.
I am quite sure everything *UFS_CARD_* refers to the other UFS host..

Konrad
Manivannan Sadhasivam Jan. 24, 2024, 8:46 a.m. UTC | #4 
On Wed, Jan 03, 2024 at 02:50:04PM +0100, Konrad Dybcio wrote:
> On 20.12.2023 09:30, Manivannan Sadhasivam wrote:
> > On Wed, Dec 20, 2023 at 01:35:27AM +0100, Konrad Dybcio wrote:
> >> On 18.12.2023 13:07, Manivannan Sadhasivam wrote:
> >>> QMP PHY used in SC8280XP requires 3 clocks:
> >>>
> >>> * ref - 19.2MHz reference clock from RPMh
> >>> * ref_aux - Auxiliary reference clock from GCC
> >>> * qref - QREF clock from GCC
> >>>
> >>> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> >>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >>> ---
> >>>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------
> >>>  1 file changed, 12 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> index cad59af7ccef..37344abbe8bf 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 {
> >>>  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
> >>>  			reg = <0 0x01d87000 0 0x1000>;
> >>>  
> >>> -			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
> >>> -				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> >>> -			clock-names = "ref", "ref_aux";
> >>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> >>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> >>> +				 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
> >> GCC_UFS_REF_CLKREF_CLK
> > 
> > I'm not sure about this CLK. So I kept it as it is until I verify it.
> I am quite sure everything *UFS_CARD_* refers to the other UFS host..
> 

We cannot infer that from the naming. There is a chance that the same clock
could be routed to MEM_PHY internally. Moreover, there is no separate "ref"
clock for MEM_PHY though.

- Mani
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index cad59af7ccef..37344abbe8bf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2256,9 +2256,12 @@  ufs_mem_phy: phy@1d87000 {
 			compatible = "qcom,sc8280xp-qmp-ufs-phy";
 			reg = <0 0x01d87000 0 0x1000>;
 
-			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
-				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-			clock-names = "ref", "ref_aux";
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
 
 			power-domains = <&gcc UFS_PHY_GDSC>;
 
@@ -2318,9 +2321,12 @@  ufs_card_phy: phy@1da7000 {
 			compatible = "qcom,sc8280xp-qmp-ufs-phy";
 			reg = <0 0x01da7000 0 0x1000>;
 
-			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
-				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
-			clock-names = "ref", "ref_aux";
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
+				 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
 
 			power-domains = <&gcc UFS_CARD_GDSC>;