| Message ID | 20240124124100.8218-8-Jonathan.Cameron@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CXL emulation fixes and minor cleanup. | expand |
On Wed, Jan 24, 2024 at 12:40:55PM +0000, Jonathan Cameron wrote: > From: Li Zhijian <lizhijian@fujitsu.com> > > cache_mem_ops.{read,write}() interprets opaque as > CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). > > Fortunately, cregs is the first member of cxl_cstate, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") > Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> > --- > hw/cxl/cxl-component-utils.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 29d477492b..9dfde6c0b3 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -199,7 +199,7 @@ void cxl_component_register_block_init(Object *obj, > /* io registers controls link which we don't care about in QEMU */ > memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", > CXL2_COMPONENT_IO_REGION_SIZE); > - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, > + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, > ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); > > memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); > -- > 2.39.2 >
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 29d477492b..9dfde6c0b3 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -199,7 +199,7 @@ void cxl_component_register_block_init(Object *obj, /* io registers controls link which we don't care about in QEMU */ memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", CXL2_COMPONENT_IO_REGION_SIZE); - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);