Message ID | 20240203165307.7806-7-aford173@gmail.com |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | soc: imx8mp: Add support for HDMI | expand |
On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > subsystem that maps all HDMI peripheral IRQs into a single upstream > IRQ line. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> This is missing your signed-off-by, and in other patches of this series your signed-off-by is not the last, as it should be. Please have a look and fix this and the other instances. Thanks for this work! Francesco
On Sun, Feb 4, 2024 at 6:00 AM Francesco Dolcini <francesco@dolcini.it> wrote: > > On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > > subsystem that maps all HDMI peripheral IRQs into a single upstream > > IRQ line. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > This is missing your signed-off-by, and in other patches of this series Opps. I thought I caught all those. > your signed-off-by is not the last, as it should be. > > Please have a look and fix this and the other instances. > OK. I have some work to do on some other portions, so I'll clean up that too. adam > Thanks for this work! Thanks for the feedback. adam > > Francesco >
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5c54073de615..5e51a766f3d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1399,6 +1399,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "hdcp", "hrv"; #power-domain-cells = <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x44>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; }; aips5: bus@30c00000 {