| Message ID | 20240122181344.258974-5-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Add support for FEAT_E2H0, or lack thereof | expand |
On Mon, Jan 22, 2024 at 06:13:38PM +0000, Marc Zyngier wrote: > ARMv9.5 has infroduced ID_AA64MMFR4_EL1 with a bunch of new features. > Add the corresponding layout. > > This is extracted from the public ARM SysReg_xml_A_profile-2023-09 > delivery, timestamped d55f5af8e09052abe92a02adf820deea2eaed717. > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Hi Marc, > On 22 Jan 2024, at 17:13, Marc Zyngier <maz@kernel.org> wrote: > > ARMv9.5 has infroduced ID_AA64MMFR4_EL1 with a bunch of new features. > Add the corresponding layout. > > This is extracted from the public ARM SysReg_xml_A_profile-2023-09 > delivery, timestamped d55f5af8e09052abe92a02adf820deea2eaed717. > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 4c9b67934367..fa3fe0856880 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1791,6 +1791,43 @@ UnsignedEnum 3:0 TCRX > EndEnum > EndSysreg > > +Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 > +Res0 63:40 > +UnsignedEnum 39:36 E3DSE > + 0b0000 NI > + 0b0001 IMP > +EndEnum > +Res0 35:28 > +SignedEnum 27:24 E2H0 > + 0b0000 IMP > + 0b1110 NI_NV1 > + 0b1111 NI > +EndEnum > +UnsignedEnum 23:20 NV_frac > + 0b0000 NV_NV2 > + 0b0001 NV2_ONLY > +EndEnum > +UnsignedEnum 19:16 FGWTE3 > + 0b0000 NI > + 0b0001 IMP > +EndEnum > +UnsignedEnum 15:12 HACDBS > + 0b0000 NI > + 0b0001 IMP > +EndEnum > +UnsignedEnum 11:8 ASID2 > + 0b0000 NI > + 0b0001 IMP > +EndEnum > +SignedEnum 7:4 EIESB > + 0b0000 NI > + 0b0001 ToEL3 > + 0b0010 ToELx > + 0b1111 ANY > +EndEnum > +Res0 3:0 > +EndSysreg > + Reviewed-by: Miguel Luis <miguel.luis@oracle.com> Would you please help me understand how the kernel would cope with E2H0’s 0b0000 value on systems prior to ARMv9.5 where a read to ID_AA64MMFR4_EL1 would be RES0 ? Thanks Miguel > Sysreg SCTLR_EL1 3 0 1 0 0 > Field 63 TIDCP > Field 62 SPINTMASK > -- > 2.39.2 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 08 Feb 2024 13:06:52 +0000, Miguel Luis <miguel.luis@oracle.com> wrote: > > Hi Marc, > > > On 22 Jan 2024, at 17:13, Marc Zyngier <maz@kernel.org> wrote: > > > > ARMv9.5 has infroduced ID_AA64MMFR4_EL1 with a bunch of new features. > > Add the corresponding layout. > > > > This is extracted from the public ARM SysReg_xml_A_profile-2023-09 > > delivery, timestamped d55f5af8e09052abe92a02adf820deea2eaed717. > > > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > --- > > arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > > index 4c9b67934367..fa3fe0856880 100644 > > --- a/arch/arm64/tools/sysreg > > +++ b/arch/arm64/tools/sysreg > > @@ -1791,6 +1791,43 @@ UnsignedEnum 3:0 TCRX > > EndEnum > > EndSysreg > > > > +Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 > > +Res0 63:40 > > +UnsignedEnum 39:36 E3DSE > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +Res0 35:28 > > +SignedEnum 27:24 E2H0 > > + 0b0000 IMP > > + 0b1110 NI_NV1 > > + 0b1111 NI > > +EndEnum > > +UnsignedEnum 23:20 NV_frac > > + 0b0000 NV_NV2 > > + 0b0001 NV2_ONLY > > +EndEnum > > +UnsignedEnum 19:16 FGWTE3 > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +UnsignedEnum 15:12 HACDBS > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +UnsignedEnum 11:8 ASID2 > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +SignedEnum 7:4 EIESB > > + 0b0000 NI > > + 0b0001 ToEL3 > > + 0b0010 ToELx > > + 0b1111 ANY > > +EndEnum > > +Res0 3:0 > > +EndSysreg > > + > > Reviewed-by: Miguel Luis <miguel.luis@oracle.com> > > Would you please help me understand how the kernel would cope with E2H0’s > 0b0000 value on systems prior to ARMv9.5 where a read to > ID_AA64MMFR4_EL1 would be RES0 ? E2H0==0 means that E2H can be set to 0. Which is what MMFR4 always indicated before the introduction of this anti-feature. On any system where E2H0 reports 0, there is no change at all for SW. Only if you want to correctly deal with a system where E2H0 reports something other than 0 would you need to do something different. Which is what this series is about, mostly. ARMv9.5 doesn't come into play, as this is an allowed anti-feature from ARMv8.1. M.
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c9b67934367..fa3fe0856880 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1791,6 +1791,43 @@ UnsignedEnum 3:0 TCRX EndEnum EndSysreg +Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 +Res0 63:40 +UnsignedEnum 39:36 E3DSE + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 35:28 +SignedEnum 27:24 E2H0 + 0b0000 IMP + 0b1110 NI_NV1 + 0b1111 NI +EndEnum +UnsignedEnum 23:20 NV_frac + 0b0000 NV_NV2 + 0b0001 NV2_ONLY +EndEnum +UnsignedEnum 19:16 FGWTE3 + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 15:12 HACDBS + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 11:8 ASID2 + 0b0000 NI + 0b0001 IMP +EndEnum +SignedEnum 7:4 EIESB + 0b0000 NI + 0b0001 ToEL3 + 0b0010 ToELx + 0b1111 ANY +EndEnum +Res0 3:0 +EndSysreg + Sysreg SCTLR_EL1 3 0 1 0 0 Field 63 TIDCP Field 62 SPINTMASK