Message ID | 20240122-ipq5332-nsscc-v4-3-19fa30019770@quicinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add NSS clock controller support for Qualcomm IPQ5332 | expand |
On Mon, Jan 22, 2024 at 11:26:59AM +0530, Kathiravan Thirumoorthy wrote:
> Add the definition for GPLL0_OUT_AUX clock.
The commit message should answer the question "Why?". Why are you
adding this clock? What consumes it?
Andrew
On 1/26/2024 1:37 AM, Andrew Lunn wrote: > On Mon, Jan 22, 2024 at 11:26:59AM +0530, Kathiravan Thirumoorthy wrote: >> Add the definition for GPLL0_OUT_AUX clock. > > The commit message should answer the question "Why?". Why are you > adding this clock? What consumes it? > > Andrew Ack, will add more details in the next spin.
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 8a405a0a96d0..24486eb47ed8 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -179,6 +179,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1