diff mbox series

clk: renesas: r8a779h0: Add SDHI clock

Message ID 3a604a6924043775c2ed0630b1c5c29be2d1a5b9.1707915642.git.geert+renesas@glider.be (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: renesas: r8a779h0: Add SDHI clock | expand

Commit Message

Geert Uytterhoeven Feb. 14, 2024, 1:01 p.m. UTC 
From: Cong Dang <cong.dang.xn@renesas.com>

Add the SDHI module clock, which is used by the SD Card/MMC Interface on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-clk for v6.9.

Changes compared to the BSP:
  - Rename "sdhi" to "sdhi0",
  - Update description to match reality.
---
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Wolfram Sang Feb. 14, 2024, 1:10 p.m. UTC | #1 
On Wed, Feb 14, 2024 at 02:01:34PM +0100, Geert Uytterhoeven wrote:
> From: Cong Dang <cong.dang.xn@renesas.com>
> 
> Add the SDHI module clock, which is used by the SD Card/MMC Interface on
> the Renesas R-Car V4M (R8A779H0) SoC.
> 
> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

> +	DEF_MOD("sdhi0",	706,	R8A779H0_CLK_SD0),

I assume this is correct because you got it to work, so:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

But documentation is unclear, the diagram above the table says sdhi0 is
707 while the table says 706. I guess you reported this already?
Geert Uytterhoeven Feb. 14, 2024, 1:44 p.m. UTC | #2 
Hi Wolfram,

On Wed, Feb 14, 2024 at 2:10 PM Wolfram Sang <wsa@kernel.org> wrote:
> On Wed, Feb 14, 2024 at 02:01:34PM +0100, Geert Uytterhoeven wrote:
> > From: Cong Dang <cong.dang.xn@renesas.com>
> >
> > Add the SDHI module clock, which is used by the SD Card/MMC Interface on
> > the Renesas R-Car V4M (R8A779H0) SoC.
> >
> > Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > +     DEF_MOD("sdhi0",        706,    R8A779H0_CLK_SD0),
>
> I assume this is correct because you got it to work, so:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> But documentation is unclear, the diagram above the table says sdhi0 is
> 707 while the table says 706. I guess you reported this already?

Thanks, I had missed that inconsistency.

After adding a dummy module clock for 707 to the clock driver, so
unused 707 gets disabled during late boot, eMMC still works.
After exchanging 706 and 707 in both the clock driver and the .dtsi,
ee140000.mmc times out waiting for SD bus idle.

So 706 must be correct.
I will report the documentation issue.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 46202e367d713d41..b95f1e5e6d470a0c 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -184,6 +184,7 @@  static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
 	DEF_MOD("i2c1",		519,	R8A779H0_CLK_S0D6_PER),
 	DEF_MOD("i2c2",		520,	R8A779H0_CLK_S0D6_PER),
 	DEF_MOD("i2c3",		521,	R8A779H0_CLK_S0D6_PER),
+	DEF_MOD("sdhi0",	706,	R8A779H0_CLK_SD0),
 	DEF_MOD("wdt1:wdt0",	907,	R8A779H0_CLK_R),
 	DEF_MOD("pfc0",		915,	R8A779H0_CLK_CP),
 	DEF_MOD("pfc1",		916,	R8A779H0_CLK_CP),