| Message ID | 20240216-clk-mv200-v1-4-a29ace29e636@outlook.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: hisilicon: add support for Hi3798MV200 | expand |
On Fri, 16 Feb 2024 19:37:54 +0800, Yang Xiwen wrote: > This SoC is similar to Hi3798CV200. > > Also document the specific DLL regs and add an example for it. > > Signed-off-by: Yang Xiwen <forbidden405@outlook.com> > --- > .../clock/hisilicon,clock-reset-generator.yaml | 36 ++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.example.dtb: /example-2/clock-reset-controller@8a22000/sap-dll@39c: failed to match any schema with compatible: ['hisilicon,sdmmc-sap-dll', 'syscon', 'simple-mfd'] Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.example.dtb: /example-2/clock-reset-controller@8a22000/sap-dll@3a4: failed to match any schema with compatible: ['hisilicon,sdmmc-sap-dll', 'syscon', 'simple-mfd'] Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.example.dtb: /example-2/clock-reset-controller@8a22000/sap-dll@3ac: failed to match any schema with compatible: ['hisilicon,sdmmc-sap-dll', 'syscon', 'simple-mfd'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240216-clk-mv200-v1-4-a29ace29e636@outlook.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Fri, Feb 16, 2024 at 07:37:54PM +0800, Yang Xiwen wrote: > This SoC is similar to Hi3798CV200. > > Also document the specific DLL regs and add an example for it. > > Signed-off-by: Yang Xiwen <forbidden405@outlook.com> > --- > .../clock/hisilicon,clock-reset-generator.yaml | 36 ++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml > index d37cd892473e..8ee844574eda 100644 > --- a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml > +++ b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml > @@ -44,12 +44,17 @@ properties: > - hisilicon,hi3519-crg > - hisilicon,hi3798cv200-crg > - hisilicon,hi3798cv200-sysctrl > + - hisilicon,hi3798mv200-crg > + - hisilicon,hi3798mv200-sysctrl > - const: syscon > - const: simple-mfd > > reg: > maxItems: 1 > > + ranges: > + maxItems: 1 > + > '#clock-cells': > const: 1 > > @@ -87,6 +92,12 @@ properties: > description: | > Reset controller for Hi3798CV200 GMAC module > > +patternProperties: > + '.*-dll@[0-9a-f]+': > + type: object > + description: | > + eMMC/SD delay-locked-loop (DLL) register subnode > + > required: > - compatible > - '#clock-cells' > @@ -137,3 +148,28 @@ examples: > #clock-cells = <1>; > }; > }; > + - | > + crg: clock-reset-controller@8a22000 { > + compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd"; > + reg = <0x8a22000 0x1000>; > + ranges = <0x0 0x8a22000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + #clock-cells = <1>; > + #reset-cells = <2>; > + > + emmc_sap_dll: sap-dll@39c { > + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; No child nodes, not a simple-mfd. > + reg = <0x39c 0x8>; I imagine you are linking to this node from the SD host controller node with some custom property. Instead of defining the register address here, link to the parent node (&crg) instead and make the offset the 2nd cell. > + }; > + > + sdio0_sap_dll: sap-dll@3a4 { > + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; > + reg = <0x3a4 0x8>; > + }; > + > + sdio1_sap_dll: sap-dll@3ac { > + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; > + reg = <0x3ac 0x8>; > + }; > + }; > > -- > 2.43.0 >
diff --git a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml index d37cd892473e..8ee844574eda 100644 --- a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml +++ b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml @@ -44,12 +44,17 @@ properties: - hisilicon,hi3519-crg - hisilicon,hi3798cv200-crg - hisilicon,hi3798cv200-sysctrl + - hisilicon,hi3798mv200-crg + - hisilicon,hi3798mv200-sysctrl - const: syscon - const: simple-mfd reg: maxItems: 1 + ranges: + maxItems: 1 + '#clock-cells': const: 1 @@ -87,6 +92,12 @@ properties: description: | Reset controller for Hi3798CV200 GMAC module +patternProperties: + '.*-dll@[0-9a-f]+': + type: object + description: | + eMMC/SD delay-locked-loop (DLL) register subnode + required: - compatible - '#clock-cells' @@ -137,3 +148,28 @@ examples: #clock-cells = <1>; }; }; + - | + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + ranges = <0x0 0x8a22000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <2>; + + emmc_sap_dll: sap-dll@39c { + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; + reg = <0x39c 0x8>; + }; + + sdio0_sap_dll: sap-dll@3a4 { + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; + reg = <0x3a4 0x8>; + }; + + sdio1_sap_dll: sap-dll@3ac { + compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd"; + reg = <0x3ac 0x8>; + }; + };