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[2/4] target/riscv: Reset CSR tcontrol when the trigger module resets

Message ID 20240216061332.50229-3-alvinga@andestech.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Implement CSR tcontrol in debug spec | expand

Commit Message

Alvin Che-Chia Chang(張哲嘉) Feb. 16, 2024, 6:13 a.m. UTC 
When the trigger module resets, reset the value of CSR tcontrol as zero.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
 target/riscv/debug.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Daniel Henrique Barboza Feb. 16, 2024, 1:22 p.m. UTC | #1 
On 2/16/24 03:13, Alvin Chang wrote:
> When the trigger module resets, reset the value of CSR tcontrol as zero.
> 
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/debug.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index e30d99cc2f..e3832a643e 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -941,5 +941,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
>           timer_del(env->itrigger_timer[i]);
>       }
>   
> +    env->tcontrol = 0;
>       env->mcontext = 0;
>   }
diff mbox series

Patch

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e30d99cc2f..e3832a643e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -941,5 +941,6 @@  void riscv_trigger_reset_hold(CPURISCVState *env)
         timer_del(env->itrigger_timer[i]);
     }
 
+    env->tcontrol = 0;
     env->mcontext = 0;
 }