| Message ID | 20240221-hisi-wdt-v3-2-9642613dc2e6@outlook.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | watchdog: sp805: add reset control support | expand |
On Wed, Feb 21, 2024 at 07:56:42PM +0800, Yang Xiwen via B4 Relay wrote: > From: Yang Xiwen <forbidden405@outlook.com> > > The reset signal needs to be deasserted before operation of sp805 > module. Document in the binding. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > Documentation/devicetree/bindings/watchdog/arm,sp805.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml > index 7aea255b301b..bd7c09ed1938 100644 > --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml > +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml > @@ -50,6 +50,10 @@ properties: > - const: wdog_clk > - const: apb_pclk > > + resets: > + maxItems: 1 > + description: WDOGRESn input reset signal for sp805 module. > + > required: > - compatible > - reg > @@ -67,4 +71,5 @@ examples: > interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&wdt_clk>, <&apb_pclk>; > clock-names = "wdog_clk", "apb_pclk"; > + resets = <&wdt_rst>; > }; > > -- > 2.43.0 >
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml index 7aea255b301b..bd7c09ed1938 100644 --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml @@ -50,6 +50,10 @@ properties: - const: wdog_clk - const: apb_pclk + resets: + maxItems: 1 + description: WDOGRESn input reset signal for sp805 module. + required: - compatible - reg @@ -67,4 +71,5 @@ examples: interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdt_clk>, <&apb_pclk>; clock-names = "wdog_clk", "apb_pclk"; + resets = <&wdt_rst>; };