| Message ID | 20240221130823.677762-4-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/21/24 03:08, Jinjie Ruan via wrote: > The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts. > > Place this in its own field within ENV, as that will > make it easier to reset from within TCG generated code. > > With the change to pstate_read/write, exception entry > and return are automatically handled. > > Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> > --- > target/arm/cpu.c | 3 +++ > target/arm/cpu.h | 9 +++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5fa86bc8d5..5e5978c302 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1104,6 +1104,9 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) > if (cpu_isar_feature(aa64_bti, cpu)) { > qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); > } > + if (cpu_isar_feature(aa64_nmi, cpu)) { > + qemu_fprintf(f, " ALLINT=%d", (psr & PSTATE_ALLINT) >> 13); > + } This is one bit -- !!(psr & ALLINT) is better We don't individually print DAIF either; why is this bit more special? > @@ -224,6 +224,7 @@ typedef struct CPUArchState { > * semantics as for AArch32, as described in the comments on each field) > * nRW (also known as M[4]) is kept, inverted, in env->aarch64 > * DAIF (exception masks) are kept in env->daif > + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint > * BTYPE is kept in env->btype > * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate > @@ -261,6 +262,7 @@ typedef struct CPUArchState { > uint32_t btype; /* BTI branch type. spsr[11:10]. */ > uint64_t daif; /* exception masks, in the bits they are in PSTATE */ > uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ > + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTATE */ Why is this split out from env->pstate? The allint bit matches the documentation for SPSR_EL1, which is how env->pstate is documented. The other exclusions have some performance imperative which I don't see for allint. r~
On 2024/2/22 2:50, Richard Henderson wrote: > On 2/21/24 03:08, Jinjie Ruan via wrote: >> The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts. >> >> Place this in its own field within ENV, as that will >> make it easier to reset from within TCG generated code. >> >> With the change to pstate_read/write, exception entry >> and return are automatically handled. >> >> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> >> --- >> target/arm/cpu.c | 3 +++ >> target/arm/cpu.h | 9 +++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 5fa86bc8d5..5e5978c302 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -1104,6 +1104,9 @@ static void aarch64_cpu_dump_state(CPUState *cs, >> FILE *f, int flags) >> if (cpu_isar_feature(aa64_bti, cpu)) { >> qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); >> } >> + if (cpu_isar_feature(aa64_nmi, cpu)) { >> + qemu_fprintf(f, " ALLINT=%d", (psr & PSTATE_ALLINT) >> 13); >> + } > > This is one bit -- !!(psr & ALLINT) is better > > We don't individually print DAIF either; why is this bit more special? That makes sense, it should be removed. > >> @@ -224,6 +224,7 @@ typedef struct CPUArchState { >> * semantics as for AArch32, as described in the comments on >> each field) >> * nRW (also known as M[4]) is kept, inverted, in env->aarch64 >> * DAIF (exception masks) are kept in env->daif >> + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint >> * BTYPE is kept in env->btype >> * SM and ZA are kept in env->svcr >> * all other bits are stored in their correct places in >> env->pstate >> @@ -261,6 +262,7 @@ typedef struct CPUArchState { >> uint32_t btype; /* BTI branch type. spsr[11:10]. */ >> uint64_t daif; /* exception masks, in the bits they are in >> PSTATE */ >> uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ >> + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in >> PSTATE */ > > Why is this split out from env->pstate? > > The allint bit matches the documentation for SPSR_EL1, which is how > env->pstate is documented. The other exclusions have some performance > imperative which I don't see for allint. It seems to me that allint is a bit like daif, so it is reasonable to maintain it separately in ENV as what daif do it. > > > r~
On 2/21/24 15:48, Jinjie Ruan wrote: >> Why is this split out from env->pstate? >> >> The allint bit matches the documentation for SPSR_EL1, which is how >> env->pstate is documented. The other exclusions have some performance >> imperative which I don't see for allint. > > It seems to me that allint is a bit like daif, so it is reasonable to > maintain it separately in ENV as what daif do it. daif is shared between aa64 pstate and aa32 cpsr; keeping those bits separate means we don't have to check the execution state in order to find them. allint has no aa32 counterpart, so it can live in pstate always. r~
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5fa86bc8d5..5e5978c302 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1104,6 +1104,9 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); } + if (cpu_isar_feature(aa64_nmi, cpu)) { + qemu_fprintf(f, " ALLINT=%d", (psr & PSTATE_ALLINT) >> 13); + } qemu_fprintf(f, "%s%s%s", (hcr & HCR_NV) ? " NV" : "", (hcr & HCR_NV1) ? " NV1" : "", diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 63f31e0d98..f9646dbbfb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -224,6 +224,7 @@ typedef struct CPUArchState { * semantics as for AArch32, as described in the comments on each field) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint * BTYPE is kept in env->btype * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate @@ -261,6 +262,7 @@ typedef struct CPUArchState { uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTATE */ uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1543,6 +1545,7 @@ FIELD(VTCR, SL2, 33, 1) #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) #define PSTATE_SSBS (1U << 12) +#define PSTATE_ALLINT (1U << 13) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) @@ -1555,7 +1558,8 @@ FIELD(VTCR, SL2, 33, 1) #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE | \ + PSTATE_ALLINT) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3t 12 @@ -1595,7 +1599,7 @@ static inline uint32_t pstate_read(CPUARMState *env) ZF = (env->ZF == 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) - | env->pstate | env->daif | (env->btype << 10); + | env->pstate | env->allint | env->daif | (env->btype << 10); } static inline void pstate_write(CPUARMState *env, uint32_t val) @@ -1604,6 +1608,7 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) env->NF = val; env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; + env->allint = val & PSTATE_ALLINT; env->daif = val & PSTATE_DAIF; env->btype = (val >> 10) & 3; env->pstate = val & ~CACHED_PSTATE_BITS;
The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts. Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 9 +++++++-- 2 files changed, 10 insertions(+), 2 deletions(-)