Message ID | 20240305070331.2151131-9-ruanjinjie@huawei.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 3/4/24 21:03, Jinjie Ruan via wrote: > Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or > CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With > CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set. > > Signed-off-by: Jinjie Ruan<ruanjinjie@huawei.com> > --- > v6: > - Verify that HCR_EL2.VF is set before checking VFNMI. > v4; > - Also handle VNMI. > v3: > - CPU_INTERRUPT_NMI do not set FIQ, so remove it. > - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. > --- > target/arm/cpu.h | 2 ++ > target/arm/helper.c | 14 ++++++++++++++ > 2 files changed, 16 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index de9446c68c..97f276559f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1467,6 +1467,8 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) +#define ISR_FS (1U << 9) +#define ISR_IS (1U << 10) #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 7cdc90e9e3..7e73edfde3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2018,15 +2018,29 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } + if (cs->interrupt_request & CPU_INTERRUPT_VNMI) { + ret |= ISR_IS; + ret |= CPSR_I; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { ret |= CPSR_I; } + + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + ret |= ISR_IS; + ret |= CPSR_I; + } } if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; + + if ((arm_hcr_el2_eff(env) & HCR_VF) && + (env->cp15.hcrx_el2 & HCRX_VFNMI)) { + ret |= ISR_FS; + } } } else { if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- v6: - Verify that HCR_EL2.VF is set before checking VFNMI. v4; - Also handle VNMI. v3: - CPU_INTERRUPT_NMI do not set FIQ, so remove it. - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+)