| Message ID | 20240306035721.2333531-1-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 3/5/24 17:56, Jinjie Ruan via wrote: > This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These > introduce support for a new category of interrupts in the architecture > which we can use to provide NMI like functionality. > > There are two modes for using this FEAT_NMI. When PSTATE.ALLINT or > PSTATE.SP & SCTLR_ELx.SCTLR_SPINTMASK is set, any entry to ELx causes all > interrupts including those with superpriority to be masked on entry to ELn > until the mask is explicitly removed by software or hardware. PSTATE.ALLINT > can be managed by software using the new register control ALLINT.ALLINT. > Independent controls are provided for this feature at each EL, usage at EL1 > should not disrupt EL2 or EL3. > > I have tested it with the following linux patches which try to support > FEAT_NMI in linux kernel: > > https://lore.kernel.org/linux-arm-kernel/Y4sH5qX5bK9xfEBp@lpieralisi/T/#mb4ba4a2c045bf72c10c2202c1dd1b82d3240dc88 > > In the test, SGI, PPI and SPI interrupts can all be set to have super priority > to be converted to a hardware NMI interrupt. The SGI is tested with kernel > IPI as NMI framework, softlockup, hardlockup and kgdb test cases, and the PPI > interrupt is tested with "perf top" command with hardware NMI enabled, and > the SPI interrupt is tested with a custom test module, in which NMI interrupts > can be received and sent normally. As far as I can see, this patch set is good to go. I'm fairly confident of the CPU side of the equation, but the GIC could use a second set of eyes. r~
Ping. On 2024/3/6 12:22, Richard Henderson wrote: > On 3/5/24 17:56, Jinjie Ruan via wrote: >> This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These >> introduce support for a new category of interrupts in the architecture >> which we can use to provide NMI like functionality. >> >> There are two modes for using this FEAT_NMI. When PSTATE.ALLINT or >> PSTATE.SP & SCTLR_ELx.SCTLR_SPINTMASK is set, any entry to ELx causes all >> interrupts including those with superpriority to be masked on entry to >> ELn >> until the mask is explicitly removed by software or hardware. >> PSTATE.ALLINT >> can be managed by software using the new register control ALLINT.ALLINT. >> Independent controls are provided for this feature at each EL, usage >> at EL1 >> should not disrupt EL2 or EL3. >> >> I have tested it with the following linux patches which try to support >> FEAT_NMI in linux kernel: >> >> https://lore.kernel.org/linux-arm-kernel/Y4sH5qX5bK9xfEBp@lpieralisi/T/#mb4ba4a2c045bf72c10c2202c1dd1b82d3240dc88 >> >> In the test, SGI, PPI and SPI interrupts can all be set to have super >> priority >> to be converted to a hardware NMI interrupt. The SGI is tested with >> kernel >> IPI as NMI framework, softlockup, hardlockup and kgdb test cases, and >> the PPI >> interrupt is tested with "perf top" command with hardware NMI enabled, >> and >> the SPI interrupt is tested with a custom test module, in which NMI >> interrupts >> can be received and sent normally. > > As far as I can see, this patch set is good to go. I'm fairly confident > of the CPU side of the equation, but the GIC could use a second set of > eyes. > > > r~
On Mon, 11 Mar 2024 at 04:00, Jinjie Ruan <ruanjinjie@huawei.com> wrote: > > Ping. Hi; this is on my list to look at, but since it's not going into 9.0 I'm afraid I'm prioritising things for softfreeze/freeze period ahead of it. I promise I'll get to it before we unfreeze for 9.1, though :-) thanks -- PMM
This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These introduce support for a new category of interrupts in the architecture which we can use to provide NMI like functionality. There are two modes for using this FEAT_NMI. When PSTATE.ALLINT or PSTATE.SP & SCTLR_ELx.SCTLR_SPINTMASK is set, any entry to ELx causes all interrupts including those with superpriority to be masked on entry to ELn until the mask is explicitly removed by software or hardware. PSTATE.ALLINT can be managed by software using the new register control ALLINT.ALLINT. Independent controls are provided for this feature at each EL, usage at EL1 should not disrupt EL2 or EL3. I have tested it with the following linux patches which try to support FEAT_NMI in linux kernel: https://lore.kernel.org/linux-arm-kernel/Y4sH5qX5bK9xfEBp@lpieralisi/T/#mb4ba4a2c045bf72c10c2202c1dd1b82d3240dc88 In the test, SGI, PPI and SPI interrupts can all be set to have super priority to be converted to a hardware NMI interrupt. The SGI is tested with kernel IPI as NMI framework, softlockup, hardlockup and kgdb test cases, and the PPI interrupt is tested with "perf top" command with hardware NMI enabled, and the SPI interrupt is tested with a custom test module, in which NMI interrupts can be received and sent normally. However, the Virtual NMI(VNMI) has not been tested. +-------------------------------------------------+ | Distributor | +-------------------------------------------------+ SPI | NMI | NMI \/ \/ +--------+ +-------+ | Redist | | Redist| +--------+ +-------+ SGI | NMI PPI | NMI \/ \/ +-------------+ +---------------+ |CPU Interface| ... | CPU Interface | +-------------+ +---------------+ | NMI | NMI \/ \/ +-----+ +-----+ | PE | | PE | +-----+ +-----+ Changes in v7: - env->cp15.hcrx_el2 -> arm_hcrx_el2_eff(). - Reorder the irqbetter() code for clarity. - Eliminate the has_superprio local variable for gicv3_get_priority(). - false -> cs->hpplpi.superprio in gicv3_redist_update_noirqset(). - 0x0 -> false in arm_gicv3_common_reset_hold(). - Clear superprio in several places for hppi, hpplpi and hppvlpi. - Add Reviewed-by. Changes in v6: - Fix DISAS_TOO_MANY to DISAS_UPDATE_EXIT for ALLINT MSR (immediate). - Verify that HCR_EL2.VF is set before checking VFNMI. - env->cp15.hcr_el2 -> arm_hcr_el2_eff(). - env->cp15.hcrx_el2 -> arm_hcrx_el2_eff(). - Not combine VFNMI with CPU_INTERRUPT_VNMI. - Implement icv_nmiar1_read(). - Put the "extract superprio info" code into gicv3_get_priority(). - Update the comment in irqbetter(). - Reset the cs->hppi.superprio to 0x0. - Set hppi.superprio to false for LPI. - Add Reviewed-by. Changes in v5: - Remove the comment for ALLINT in cpu.h. - Merge allint_check() to msr_i_allint to clear the ALLINT MSR (immediate) implementation. - Rename msr_i_allint() to msr_set_allint_el1() to make it clearer. - Drop the & 1 in trans_MSR_i_ALLINT(). - Add Reviewed-by. Changes in v4: - Handle VNMI within the CPU and the GIC. - Keep PSTATE.ALLINT in env->pstate but not env->allint. - Fix the ALLINT MSR (immediate) decodetree implementation. - Accept NMI unconditionally for arm_cpu_has_work() but add comment. - Improve nmi mask in arm_excp_unmasked(). - Make the GICR_INMIR0 and GICD_INMIR implementation more clearer. - Improve ICC_NMIAR1_EL1 implementation - Extract gicv3_get_priority() to avoid priority code repetition. - Add Reviewed-by. Changes in v3: - Remove the FIQ NMI. - Adjust the patches Sequence. - Reomve the patch "Set pstate.ALLINT in arm_cpu_reset_hold". - Check whether support FEAT_NMI and FEAT_GICv3 for FEAT_GICv3_NMI. - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. - Not include NMI logic when FEAT_NMI or SCTLR_ELx.NMI not enabled. - Refator nmi mask in arm_excp_unmasked(). - Add VNMI definitions, add HCRX_VINMI and HCRX_VFNMI support in HCRX_EL2. - Add Reviewed-by and Acked-by. - Update the commit message. Changes in v2: - Break up the patches so that each one does only one thing. - Remove the command line option and just implement it in "max" cpu. Jinjie Ruan (23): target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI target/arm: Add PSTATE.ALLINT target/arm: Add support for FEAT_NMI, Non-maskable Interrupt target/arm: Implement ALLINT MSR (immediate) target/arm: Support MSR access to ALLINT target/arm: Add support for Non-maskable Interrupt target/arm: Add support for NMI in arm_phys_excp_target_el() target/arm: Handle IS/FS in ISR_EL1 for NMI target/arm: Handle PSTATE.ALLINT on taking an exception hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU hw/intc/arm_gicv3: Add external IRQ lines for NMI target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() hw/intc/arm_gicv3: Add irq superpriority information hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 hw/intc/arm_gicv3: Implement GICD_INMIR hw/intc: Enable FEAT_GICv3_NMI Feature hw/intc/arm_gicv3: Add NMI handling CPU interface registers hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() hw/intc/arm_gicv3: Implement NMI interrupt prioirty hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Report the VNMI interrupt target/arm: Add FEAT_NMI to max hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC docs/system/arm/emulation.rst | 1 + hw/arm/virt.c | 25 +++++- hw/intc/arm_gicv3.c | 69 +++++++++++++--- hw/intc/arm_gicv3_common.c | 10 +++ hw/intc/arm_gicv3_cpuif.c | 125 ++++++++++++++++++++++++++--- hw/intc/arm_gicv3_dist.c | 36 +++++++++ hw/intc/arm_gicv3_redist.c | 22 +++++ hw/intc/gicv3_internal.h | 8 ++ hw/intc/trace-events | 2 + include/hw/intc/arm_gic_common.h | 2 + include/hw/intc/arm_gicv3_common.h | 7 ++ target/arm/cpu-features.h | 5 ++ target/arm/cpu-qom.h | 4 +- target/arm/cpu.c | 85 ++++++++++++++++++-- target/arm/cpu.h | 7 ++ target/arm/helper.c | 67 ++++++++++++++++ target/arm/internals.h | 12 +++ target/arm/tcg/a64.decode | 1 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/helper-a64.c | 12 +++ target/arm/tcg/helper-a64.h | 1 + target/arm/tcg/translate-a64.c | 19 +++++ 22 files changed, 494 insertions(+), 27 deletions(-)