diff mbox series

[v1,4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

Message ID 20240312123627.9285-5-andy.chiu@sifive.com (mailing list archive)
State Superseded
Headers show
Series Support Zve32[xf] and Zve64[xfd] Vector subextensions | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-4-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-4-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-4-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-4-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-4-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-4-test-6 fail .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-4-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-4-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-4-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-4-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-4-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-4-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Andy Chiu March 12, 2024, 12:36 p.m. UTC 
Multiple Vector subextensions are added. Also, the patch takes care of
the dependencies of Vector subextensions by macro expansions. So, if
some "embedded" platform only reports "zve64f" on the ISA string, the
parser is able to expand it to zve32x zve32f zve64x and zve64f.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/include/asm/hwcap.h |  5 +++++
 arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 1 deletion(-)

Comments

Clément Léger March 12, 2024, 12:51 p.m. UTC | #1 
On 12/03/2024 13:36, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),

Hi Andy,

Nit: Since RISCV_ISA_EXT_ZVE32F is already used here as .id, you don't
need to insert it in the riscv_zve32f_exts array. It won't hurt but the
existing extensions that uses the __RISCV_ISA_EXT_SUPERSET() macro don't
do that.

> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),

Ditto for the last 3 __RISCV_ISA_EXT_SUPERSET().

Apart from that, it looks good !

Thanks,

Clément

>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
Conor Dooley March 12, 2024, 1:05 p.m. UTC | #2 
On Tue, Mar 12, 2024 at 08:36:25PM +0800, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

These new extensions need to be added to the dt-bindings.

> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Andy Chiu March 13, 2024, 3:34 a.m. UTC | #3 
On Tue, Mar 12, 2024 at 8:51 PM Clément Léger <cleger@rivosinc.com> wrote:
>
>
>
> On 12/03/2024 13:36, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
>
> Hi Andy,
>
> Nit: Since RISCV_ISA_EXT_ZVE32F is already used here as .id, you don't
> need to insert it in the riscv_zve32f_exts array. It won't hurt but the
> existing extensions that uses the __RISCV_ISA_EXT_SUPERSET() macro don't
> do that.
>

Noted, I will update it in the next revision.

Thanks,
Andy

> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>
> Ditto for the last 3 __RISCV_ISA_EXT_SUPERSET().
>
> Apart from that, it looks good !
>
> Thanks,
>
> Clément
>
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
Samuel Holland March 13, 2024, 4:01 a.m. UTC | #4 
Hi Andy,

On 2024-03-12 7:36 AM, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),

You can use riscv_zve64d_exts here (or #define riscv_v_exts riscv_zve64d_exts)
to avoid allocating a duplicate subextension list.

Regards,
Samuel

>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
Andy Chiu March 13, 2024, 7:03 a.m. UTC | #5 
On Wed, Mar 13, 2024 at 12:01 PM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> Hi Andy,
>
> On 2024-03-12 7:36 AM, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>
> You can use riscv_zve64d_exts here (or #define riscv_v_exts riscv_zve64d_exts)
> to avoid allocating a duplicate subextension list.

Yes, I should do that, will change that in v2

>
> Regards,
> Samuel
>
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
>

Thanks!
Andy
Andy Chiu March 13, 2024, 7:04 a.m. UTC | #6 
On Tue, Mar 12, 2024 at 9:05 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Mar 12, 2024 at 08:36:25PM +0800, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
>
> These new extensions need to be added to the dt-bindings.

I am adding a patch for dt-binding after this in v2.

>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> > --
> > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

Thanks!
Andy
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5340f818746b..24efea44f1ab 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -80,6 +80,11 @@ 
 #define RISCV_ISA_EXT_ZFA		71
 #define RISCV_ISA_EXT_ZTSO		72
 #define RISCV_ISA_EXT_ZACAS		73
+#define RISCV_ISA_EXT_ZVE32X		74
+#define RISCV_ISA_EXT_ZVE32F		75
+#define RISCV_ISA_EXT_ZVE64X		76
+#define RISCV_ISA_EXT_ZVE64F		77
+#define RISCV_ISA_EXT_ZVE64D		78
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 8986ceb58188..3aa0df3f3b41 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -201,6 +201,40 @@  static const unsigned int riscv_zvbb_exts[] = {
 	RISCV_ISA_EXT_ZVKB
 };
 
+#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE32F,		\
+	RISCV_ISA_EXT_ZVE32X,
+
+#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE64F,		\
+	RISCV_ISA_EXT_ZVE64X,		\
+	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
+
+#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE64D,		\
+	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
+
+static const unsigned int riscv_zve32f_exts[] = {
+	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64f_exts[] = {
+	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64d_exts[] = {
+	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64x_exts[] = {
+	RISCV_ISA_EXT_ZVE32X,
+	RISCV_ISA_EXT_ZVE64X
+};
+
+static const unsigned int riscv_v_exts[] = {
+	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -248,7 +282,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
 	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
 	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
-	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
+	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
 	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
 	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
@@ -283,6 +317,11 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
 	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
+	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
+	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
+	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
+	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
 	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
 	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),