diff mbox series

[v7,3/6] cpufreq:amd-pstate: get pstate transition delay and latency value from ACPI tables

Message ID 705e1a21a6a9d91a7ac67526c55c2961318ad678.1710323410.git.perry.yuan@amd.com (mailing list archive)
State Changes Requested, archived
Headers show
Series AMD Pstate Fixes And Enhancements | expand

Commit Message

Yuan, Perry March 13, 2024, 9:59 a.m. UTC
make pstate driver initially retrieve the P-state transition delay and latency
values from the BIOS ACPI tables which has more reasonable delay and latency
values according to the platform design and requirements.

Previously there values were hardcoded at specific value which may
have conflicted with platform and it might not reflect the most accurate or
optimized setting for the processor.

[054h 0084   8]                Preserve Mask : FFFFFFFF00000000
[05Ch 0092   8]                   Write Mask : 0000000000000001
[064h 0100   4]              Command Latency : 00000FA0
[068h 0104   4]          Maximum Access Rate : 0000EA60
[06Ch 0108   2]      Minimum Turnaround Time : 0000

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

Comments

Gautham R. Shenoy March 14, 2024, 6:23 a.m. UTC | #1
On Wed, Mar 13, 2024 at 05:59:15PM +0800, Perry Yuan wrote:
> make pstate driver initially retrieve the P-state transition delay and latency
> values from the BIOS ACPI tables which has more reasonable delay and latency
> values according to the platform design and requirements.
> 
> Previously there values were hardcoded at specific value which may
> have conflicted with platform and it might not reflect the most accurate or
> optimized setting for the processor.
> 
> [054h 0084   8]                Preserve Mask : FFFFFFFF00000000
> [05Ch 0092   8]                   Write Mask : 0000000000000001
> [064h 0100   4]              Command Latency : 00000FA0
> [068h 0104   4]          Maximum Access Rate : 0000EA60
> [06Ch 0108   2]      Minimum Turnaround Time : 0000
> 
> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> Signed-off-by: Perry Yuan <perry.yuan@amd.com>

Looks good to me.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>

> ---
>  drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 6db9256f42c0..ec6259957d25 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -827,6 +827,36 @@ static void amd_pstate_update_limits(unsigned int cpu)
>  	mutex_unlock(&amd_pstate_driver_lock);
>  }
>  
> +/**
> + * Get pstate transition delay time from ACPI tables that firmware set
> + * instead of using hardcode value directly.
> + */
> +static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
> +{
> +	u32 transition_delay_ns;
> +
> +	transition_delay_ns = cppc_get_transition_latency(cpu);
> +	if (transition_delay_ns == CPUFREQ_ETERNAL)
> +		return AMD_PSTATE_TRANSITION_DELAY;
> +
> +	return transition_delay_ns / NSEC_PER_USEC;
> +}
> +
> +/**
> + * Get pstate transition latency value from ACPI tables that firmware set
> + * instead of using hardcode value directly.
> + */
> +static u32 amd_pstate_get_transition_latency(unsigned int cpu)
> +{
> +	u32 transition_latency;
> +
> +	transition_latency = cppc_get_transition_latency(cpu);
> +	if (transition_latency  == CPUFREQ_ETERNAL)
> +		return AMD_PSTATE_TRANSITION_LATENCY;
> +
> +	return transition_latency;
> +}
> +
>  static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>  {
>  	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
> @@ -867,8 +897,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>  		goto free_cpudata1;
>  	}
>  
> -	policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY;
> -	policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
> +	policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu);
> +	policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu);
>  
>  	policy->min = min_freq;
>  	policy->max = max_freq;
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 6db9256f42c0..ec6259957d25 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -827,6 +827,36 @@  static void amd_pstate_update_limits(unsigned int cpu)
 	mutex_unlock(&amd_pstate_driver_lock);
 }
 
+/**
+ * Get pstate transition delay time from ACPI tables that firmware set
+ * instead of using hardcode value directly.
+ */
+static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
+{
+	u32 transition_delay_ns;
+
+	transition_delay_ns = cppc_get_transition_latency(cpu);
+	if (transition_delay_ns == CPUFREQ_ETERNAL)
+		return AMD_PSTATE_TRANSITION_DELAY;
+
+	return transition_delay_ns / NSEC_PER_USEC;
+}
+
+/**
+ * Get pstate transition latency value from ACPI tables that firmware set
+ * instead of using hardcode value directly.
+ */
+static u32 amd_pstate_get_transition_latency(unsigned int cpu)
+{
+	u32 transition_latency;
+
+	transition_latency = cppc_get_transition_latency(cpu);
+	if (transition_latency  == CPUFREQ_ETERNAL)
+		return AMD_PSTATE_TRANSITION_LATENCY;
+
+	return transition_latency;
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
@@ -867,8 +897,8 @@  static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 		goto free_cpudata1;
 	}
 
-	policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY;
-	policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
+	policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu);
+	policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu);
 
 	policy->min = min_freq;
 	policy->max = max_freq;