@@ -43,6 +43,7 @@
#define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
/* COMPHY registers */
+#define COMPHY_GBE_PHY_MAX_REGS 512
#define COMPHY_POWER_PLL_CTRL 0x01
#define PU_IVREF_BIT BIT(15)
#define PU_PLL_BIT BIT(14)
@@ -296,7 +297,7 @@ static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {
};
/* 40M1G25 mode init data */
-static u16 gbe_phy_init[512] = {
+static u16 gbe_phy_init[COMPHY_GBE_PHY_MAX_REGS] = {
/* 0 1 2 3 4 5 6 7 */
/*-----------------------------------------------------------*/
/* 8 9 A B C D E F */
@@ -603,7 +604,7 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
u16 val;
fix_idx = 0;
- for (addr = 0; addr < 512; addr++) {
+ for (addr = 0; addr < COMPHY_GBE_PHY_MAX_REGS; addr++) {
/*
* All PHY register values are defined in full for 3.125Gbps
* SERDES speed. The values required for 1.25 Gbps are almost
Replace hardcoded 'gbe_phy_init' array size with defined value. Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation") Signed-off-by: Mikhail Kobuk <m.kobuk@ispras.ru> --- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)