diff mbox series

[v6,2/9] x86/cpu: KVM: Move macro to encode PAT value to common header

Message ID 20240309012725.1409949-3-seanjc@google.com (mailing list archive)
State New, archived
Headers show
Series x86/cpu: KVM: Clean up PAT and VMX macros | expand

Commit Message

Sean Christopherson March 9, 2024, 1:27 a.m. UTC 
Move pat/memtype.c's PAT() macro to msr-index.h as PAT_VALUE(), and use it
in KVM to define the default (Power-On / RESET) PAT value instead of open
coding an inscrutable magic number.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 arch/x86/include/asm/msr-index.h |  6 ++++++
 arch/x86/kvm/x86.h               |  3 ++-
 arch/x86/mm/pat/memtype.c        | 12 +++---------
 3 files changed, 11 insertions(+), 10 deletions(-)

Comments

Huang, Kai March 27, 2024, 11:21 a.m. UTC | #1 
On Fri, 2024-03-08 at 17:27 -0800, Sean Christopherson wrote:
> Move pat/memtype.c's PAT() macro to msr-index.h as PAT_VALUE(), and use it
> in KVM to define the default (Power-On / RESET) PAT value instead of open
> coding an inscrutable magic number.
> 
> No functional change intended.
> 
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> 

Reviewed-by: Kai Huang <kai.huang@intel.com>
Xiaoyao Li April 1, 2024, 5:28 a.m. UTC | #2 
On 3/9/2024 9:27 AM, Sean Christopherson wrote:
> Move pat/memtype.c's PAT() macro to msr-index.h as PAT_VALUE(), and use it
> in KVM to define the default (Power-On / RESET) PAT value instead of open
> coding an inscrutable magic number.
> 
> No functional change intended.
> 
> Signed-off-by: Sean Christopherson <seanjc@google.com>

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Huang, Kai April 3, 2024, 9:03 p.m. UTC | #3 
>   void __init pat_bp_init(void)
>   {
>   	struct cpuinfo_x86 *c = &boot_cpu_data;
> -#define PAT(p0, p1, p2, p3, p4, p5, p6, p7)				\
> -	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\
> -	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\
> -	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\
> -	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))
> -
>   
>   	if (!IS_ENABLED(CONFIG_X86_PAT))
>   		pr_info_once("x86/PAT: PAT support disabled because CONFIG_X86_PAT is disabled in the kernel.\n");
> @@ -281,7 +275,7 @@ void __init pat_bp_init(void)
>   		 * NOTE: When WC or WP is used, it is redirected to UC- per
>   		 * the default setup in __cachemode2pte_tbl[].
>   		 */
> -		pat_msr_val = PAT(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);
> +		pat_msr_val = PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);
>   	}
>   
>   	/*
> @@ -321,7 +315,7 @@ void __init pat_bp_init(void)
>   		 * NOTE: When WT or WP is used, it is redirected to UC- per
>   		 * the default setup in __cachemode2pte_tbl[].
>   		 */
> -		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);
> +		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);
>   	} else {
>   		/*
>   		 * Full PAT support.  We put WT in slot 7 to improve
> @@ -349,7 +343,7 @@ void __init pat_bp_init(void)
>   		 * The reserved slots are unused, but mapped to their
>   		 * corresponding types in the presence of PAT errata.
>   		 */
> -		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);
> +		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);
>   	}
>   
>   	memory_caching_control |= CACHE_PAT;

I found there's one "#undef PAT" at the end of pat_bp_init() and it 
should be removed:

void __init pat_bp_init(void)
{
         struct cpuinfo_x86 *c = &boot_cpu_data;
#define PAT(p0, p1, p2, p3, p4, p5, p6, p7)                     \
         (((u64)PAT_ ## p0) | ((u64)PAT_ ## p1 << 8) |           \
         ((u64)PAT_ ## p2 << 16) | ((u64)PAT_ ## p3 << 24) |     \
         ((u64)PAT_ ## p4 << 32) | ((u64)PAT_ ## p5 << 40) |     \
         ((u64)PAT_ ## p6 << 48) | ((u64)PAT_ ## p7 << 56))

	...

         memory_caching_control |= CACHE_PAT;

         init_cache_modes(pat_msr_val);
#undef PAT
}
diff mbox series

Patch

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 29f0ea78e41c..af71f8bb76ae 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -352,6 +352,12 @@ 
 
 #define MSR_IA32_CR_PAT			0x00000277
 
+#define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7)			\
+	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\
+	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\
+	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\
+	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))
+
 #define MSR_IA32_DEBUGCTLMSR		0x000001d9
 #define MSR_IA32_LASTBRANCHFROMIP	0x000001db
 #define MSR_IA32_LASTBRANCHTOIP		0x000001dc
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index a8b71803777b..753403639e72 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -87,7 +87,8 @@  static inline unsigned int __shrink_ple_window(unsigned int val,
 	return max(val, min);
 }
 
-#define MSR_IA32_CR_PAT_DEFAULT  0x0007040600070406ULL
+#define MSR_IA32_CR_PAT_DEFAULT	\
+	PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC)
 
 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
 int kvm_check_nested_events(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 3e0ba044925f..f2dedddfbaf2 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -245,12 +245,6 @@  void pat_cpu_init(void)
 void __init pat_bp_init(void)
 {
 	struct cpuinfo_x86 *c = &boot_cpu_data;
-#define PAT(p0, p1, p2, p3, p4, p5, p6, p7)				\
-	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\
-	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\
-	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\
-	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))
-
 
 	if (!IS_ENABLED(CONFIG_X86_PAT))
 		pr_info_once("x86/PAT: PAT support disabled because CONFIG_X86_PAT is disabled in the kernel.\n");
@@ -281,7 +275,7 @@  void __init pat_bp_init(void)
 		 * NOTE: When WC or WP is used, it is redirected to UC- per
 		 * the default setup in __cachemode2pte_tbl[].
 		 */
-		pat_msr_val = PAT(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);
+		pat_msr_val = PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);
 	}
 
 	/*
@@ -321,7 +315,7 @@  void __init pat_bp_init(void)
 		 * NOTE: When WT or WP is used, it is redirected to UC- per
 		 * the default setup in __cachemode2pte_tbl[].
 		 */
-		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);
+		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);
 	} else {
 		/*
 		 * Full PAT support.  We put WT in slot 7 to improve
@@ -349,7 +343,7 @@  void __init pat_bp_init(void)
 		 * The reserved slots are unused, but mapped to their
 		 * corresponding types in the presence of PAT errata.
 		 */
-		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);
+		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);
 	}
 
 	memory_caching_control |= CACHE_PAT;