| Message ID | 20240403180226.1641383-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [1/3] net: dsa: microchip: lan9372: fix TX PHY access | expand |
On Wed, 2024-04-03 at 20:02 +0200, Lucas Stach wrote: > [Some people who received this message don't often get email from > l.stach@pengutronix.de. Learn why this is important at > https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On the LAN9372 the 4th internal PHY is a TX PHY instead of a T1 PHY. > TX PHYs have a different base register offset. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> As it is targetted net, it should have fixes tag. > --- > drivers/net/dsa/microchip/lan937x_main.c | 3 +++ > drivers/net/dsa/microchip/lan937x_reg.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/net/dsa/microchip/lan937x_main.c > b/drivers/net/dsa/microchip/lan937x_main.c > index b479a628b1ae..6a20cbacc513 100644 > --- a/drivers/net/dsa/microchip/lan937x_main.c > +++ b/drivers/net/dsa/microchip/lan937x_main.c > @@ -55,6 +55,9 @@ static int lan937x_vphy_ind_addr_wr(struct > ksz_device *dev, int addr, int reg) > u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; > u16 temp; > > + if (dev->info->chip_id == LAN9372_CHIP_ID && addr == 3) > + addr_base = REG_PORT_TX_PHY_CTRL_BASE; LAN9371 is similar to LAN9372, it also have 4th internal phy as Tx Phy. Can you please add LAN9371 as well here. > + > /* get register address based on the logical port */ > temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); > > diff --git a/drivers/net/dsa/microchip/lan937x_reg.h > b/drivers/net/dsa/microchip/lan937x_reg.h > index 45b606b6429f..7ecada924023 100644 > --- a/drivers/net/dsa/microchip/lan937x_reg.h > +++ b/drivers/net/dsa/microchip/lan937x_reg.h > @@ -147,6 +147,7 @@ > > /* 1 - Phy */ > #define REG_PORT_T1_PHY_CTRL_BASE 0x0100 > +#define REG_PORT_TX_PHY_CTRL_BASE 0x0280 > > /* 3 - xMII */ > #define PORT_SGMII_SEL BIT(7) > -- > 2.39.2 >
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index b479a628b1ae..6a20cbacc513 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -55,6 +55,9 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; u16 temp; + if (dev->info->chip_id == LAN9372_CHIP_ID && addr == 3) + addr_base = REG_PORT_TX_PHY_CTRL_BASE; + /* get register address based on the logical port */ temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 45b606b6429f..7ecada924023 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -147,6 +147,7 @@ /* 1 - Phy */ #define REG_PORT_T1_PHY_CTRL_BASE 0x0100 +#define REG_PORT_TX_PHY_CTRL_BASE 0x0280 /* 3 - xMII */ #define PORT_SGMII_SEL BIT(7)
On the LAN9372 the 4th internal PHY is a TX PHY instead of a T1 PHY. TX PHYs have a different base register offset. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/net/dsa/microchip/lan937x_main.c | 3 +++ drivers/net/dsa/microchip/lan937x_reg.h | 1 + 2 files changed, 4 insertions(+)