| Message ID | 20240322130646.1016630-1-marcel@ziswiler.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | phy: freescale: imx8m-pcie: facing pcie link-up instability | expand |
Hi Marcel, On Fri, Mar 22, 2024 at 10:07 AM Marcel Ziswiler <marcel@ziswiler.com> wrote: > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > While this setup has proven very stable overall we noticed upstream on > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > that old downstream stuff was quite different, I first also tried NXP's > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > fairly vanilla, however, also there the PCIe link-up was not stable. > Comparing and debugging I noticed that upstream explicitly configures > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > Unfortunately, the TRM does not mention any further details about this > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > from NXP could further comment on this? > > BTW: On the i.MX 8M Plus we have not seen any issues with PCIe with the > exact same setup which is why I left it unchanged. > > [1] https://www.delock.com/produkt/95233/merkmale.html > [2] https://github.com/nxp-imx/linux-imx/blob/lf-5.15.71-2.2.0/drivers/pci/controller/dwc/pci-imx6.c#L1548 The detailed information above is important. It should be in the commit log of the patch IMHO. Thanks for the fix.
On Fri, 22 Mar 2024 14:06:31 +0100, Marcel Ziswiler wrote: > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > While this setup has proven very stable overall we noticed upstream on > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > that old downstream stuff was quite different, I first also tried NXP's > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > fairly vanilla, however, also there the PCIe link-up was not stable. > Comparing and debugging I noticed that upstream explicitly configures > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > Unfortunately, the TRM does not mention any further details about this > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > from NXP could further comment on this? > > [...] Applied, thanks! [1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability commit: 3a161017f1de55cc48be81f6156004c151f32677 Best regards,
Hi Vinod On Sat, 2024-04-06 at 14:48 +0530, Vinod Koul wrote: > > On Fri, 22 Mar 2024 14:06:31 +0100, Marcel Ziswiler wrote: > > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > > While this setup has proven very stable overall we noticed upstream on > > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > > that old downstream stuff was quite different, I first also tried NXP's > > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > > fairly vanilla, however, also there the PCIe link-up was not stable. > > Comparing and debugging I noticed that upstream explicitly configures > > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > > Unfortunately, the TRM does not mention any further details about this > > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > > from NXP could further comment on this? > > > > [...] > > Applied, thanks! > > [1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability > commit: 3a161017f1de55cc48be81f6156004c151f32677 Sorry, but it is slightly confusing whether v1 or v2 now got applied. I believe v1 but then only the commit messages differ. However, please note that only v2 included information on how to proceed concerning backporting to stable 6.1.x. Thanks! > Best regards, > -- > -Vinod Cheers Marcel
On 07-04-24, 22:22, Marcel Ziswiler wrote: > Hi Vinod > > On Sat, 2024-04-06 at 14:48 +0530, Vinod Koul wrote: > > > > On Fri, 22 Mar 2024 14:06:31 +0100, Marcel Ziswiler wrote: > > > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > > > While this setup has proven very stable overall we noticed upstream on > > > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > > > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > > > that old downstream stuff was quite different, I first also tried NXP's > > > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > > > fairly vanilla, however, also there the PCIe link-up was not stable. > > > Comparing and debugging I noticed that upstream explicitly configures > > > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > > > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > > > Unfortunately, the TRM does not mention any further details about this > > > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > > > from NXP could further comment on this? > > > > > > [...] > > > > Applied, thanks! > > > > [1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability > > commit: 3a161017f1de55cc48be81f6156004c151f32677 > > Sorry, but it is slightly confusing whether v1 or v2 now got applied. I believe v1 but then only the commit > messages differ. However, please note that only v2 included information on how to proceed concerning > backporting to stable 6.1.x. V2 was picked, you can check phy tree Somehow b4 sent email for v1 as well
Hi Vinod On Fri, 2024-04-12 at 16:54 +0530, Vinod Koul wrote: > On 07-04-24, 22:22, Marcel Ziswiler wrote: > > Hi Vinod > > > > On Sat, 2024-04-06 at 14:48 +0530, Vinod Koul wrote: > > > > > > On Fri, 22 Mar 2024 14:06:31 +0100, Marcel Ziswiler wrote: > > > > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > > > > While this setup has proven very stable overall we noticed upstream on > > > > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > > > > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > > > > that old downstream stuff was quite different, I first also tried NXP's > > > > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > > > > fairly vanilla, however, also there the PCIe link-up was not stable. > > > > Comparing and debugging I noticed that upstream explicitly configures > > > > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > > > > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > > > > Unfortunately, the TRM does not mention any further details about this > > > > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > > > > from NXP could further comment on this? > > > > > > > > [...] > > > > > > Applied, thanks! > > > > > > [1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability > > > commit: 3a161017f1de55cc48be81f6156004c151f32677 > > > > Sorry, but it is slightly confusing whether v1 or v2 now got applied. I believe v1 but then only the commit > > messages differ. However, please note that only v2 included information on how to proceed concerning > > backporting to stable 6.1.x. > > V2 was picked, you can check phy tree Okay, however it uses the commit message of v1 which is rather strange. > Somehow b4 sent email for v1 as well Cheers Marcel
From: Marcel Ziswiler <marcel.ziswiler@toradex.com> In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. While this setup has proven very stable overall we noticed upstream on the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As that old downstream stuff was quite different, I first also tried NXP's latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is fairly vanilla, however, also there the PCIe link-up was not stable. Comparing and debugging I noticed that upstream explicitly configures the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). Unfortunately, the TRM does not mention any further details about this register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody from NXP could further comment on this? BTW: On the i.MX 8M Plus we have not seen any issues with PCIe with the exact same setup which is why I left it unchanged. [1] https://www.delock.com/produkt/95233/merkmale.html [2] https://github.com/nxp-imx/linux-imx/blob/lf-5.15.71-2.2.0/drivers/pci/controller/dwc/pci-imx6.c#L1548 Marcel Ziswiler (1): phy: freescale: imx8m-pcie: fix pcie link-up instability drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.44.0