| Message ID | 20240411130150.128107-2-cassel@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | rockchip pcie3-phy separate refclk support | expand |
On 11/04/2024 15:01, Niklas Cassel wrote: > From the RK3588 Technical Reference Manual, Part1, > section 6.19 PCIe3PHY_GRF Register Description: > "rxX_cmn_refclk_mode" > RX common reference clock mode for lane X. This mode should be enabled > only when the far-end and near-end devices are running with a common > reference clock. > > The hardware reset value for this field is 0x1 (enabled). > Note that this register field is only available on RK3588, not on RK3568. > > The link training either fails or is highly unstable (link state will jump > continuously between L0 and recovery) when this mode is enabled while > using an endpoint running in Separate Reference Clock with No SSC (SRNS) > mode or Separate Reference Clock with SSC (SRIS) mode. > (Which is usually the case when using a real SoC as endpoint, e.g. the > RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index c4fbffcde6e4..ba67dca5a446 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -54,6 +54,16 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the syscon managing the pipe "general register files" + rockchip,rx-common-refclk-mode: + description: which lanes (by position) should be configured to run in + RX common reference clock mode. 0 means disabled, 1 means enabled. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + items: + minimum: 0 + maximum: 1 + required: - compatible - reg
From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add a rockchip specific property to enable/disable the rxX_cmn_refclk_mode per lane. (Since this PHY supports bifurcation.) Signed-off-by: Niklas Cassel <cassel@kernel.org> --- .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)