| Message ID | 20240411-dev-charlie-support_thead_vector_6_9-v1-1-4af9815ec746@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Support vendor extensions and xtheadvector | expand |
On Thu, Apr 11, 2024 at 09:11:07PM -0700, Charlie Jenkins wrote: > vendorid and marchid are required during devicetree parsing to determine > known hardware capabilities. This parsing happens before the whole > system has booted, so only the boot hart is online and able to report > the value of its vendorid and archid. I'll comment on the kernel patch, but this is not needed. > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d87dd50f1a4b..c21d7374636c 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -94,6 +94,17 @@ properties: > description: > The blocksize in bytes for the Zicboz cache operations. > > + riscv,vendorid: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Same value as the mvendorid CSR. > + > + riscv,archid: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Same value as the marchid CSR. > + > + > # RISC-V has multiple properties for cache op block sizes as the sizes > # differ between individual CBO extensions > cache-op-block-size: false > > -- > 2.44.0 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c21d7374636c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -94,6 +94,17 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. + riscv,vendorid: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Same value as the mvendorid CSR. + + riscv,archid: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Same value as the marchid CSR. + + # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false
vendorid and marchid are required during devicetree parsing to determine known hardware capabilities. This parsing happens before the whole system has booted, so only the boot hart is online and able to report the value of its vendorid and archid. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)