| Message ID | 20240414182706.655270-1-detlev.casanova@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: vop2: Do not divide height twice for YUV | expand |
Hi, On 4/15/24 02:27, Detlev Casanova wrote: > For the cbcr format, gt2 and gt4 are computed again after src_h has been > divided by vsub. > > As src_h as already been divided by 2 before, introduce cbcr_src_h and > cbcr_src_w to keep a copy of those values to be used for cbcr gt2 and > gt4 computation. > > This fixes yuv planes being unaligned vertically when down scaling to > 1080 pixels from 2160. > > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") Acked-by: Andy Yan <andy.yan@rock-chips.com> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 22 +++++++++++--------- > 1 file changed, 12 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > index fdd768bbd487c..62ebbdb16253d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > @@ -706,6 +706,8 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, > const struct drm_format_info *info; > u16 hor_scl_mode, ver_scl_mode; > u16 hscl_filter_mode, vscl_filter_mode; > + uint16_t cbcr_src_w = src_w; > + uint16_t cbcr_src_h = src_h; > u8 gt2 = 0; > u8 gt4 = 0; > u32 val; > @@ -763,27 +765,27 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, > vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); > > if (info->is_yuv) { > - src_w /= info->hsub; > - src_h /= info->vsub; > + cbcr_src_w /= info->hsub; > + cbcr_src_h /= info->vsub; > > gt4 = 0; > gt2 = 0; > > - if (src_h >= (4 * dst_h)) { > + if (cbcr_src_h >= (4 * dst_h)) { > gt4 = 1; > - src_h >>= 2; > - } else if (src_h >= (2 * dst_h)) { > + cbcr_src_h >>= 2; > + } else if (cbcr_src_h >= (2 * dst_h)) { > gt2 = 1; > - src_h >>= 1; > + cbcr_src_h >>= 1; > } > > - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); > - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); > + hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); > + ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); > > - val = vop2_scale_factor(src_w, dst_w); > + val = vop2_scale_factor(cbcr_src_w, dst_w); > vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); > > - val = vop2_scale_factor(src_h, dst_h); > + val = vop2_scale_factor(cbcr_src_h, dst_h); > vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); > > vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
On Sun, 14 Apr 2024 14:27:06 -0400, Detlev Casanova wrote: > For the cbcr format, gt2 and gt4 are computed again after src_h has been > divided by vsub. > > As src_h as already been divided by 2 before, introduce cbcr_src_h and > cbcr_src_w to keep a copy of those values to be used for cbcr gt2 and > gt4 computation. > > [...] Applied, thanks! [1/1] drm: vop2: Do not divide height twice for YUV commit: e80c219f52861e756181d7f88b0d341116daac2b But changed the subject to drm/rockchip: vop2: ..... Best regards,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index fdd768bbd487c..62ebbdb16253d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -706,6 +706,8 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, const struct drm_format_info *info; u16 hor_scl_mode, ver_scl_mode; u16 hscl_filter_mode, vscl_filter_mode; + uint16_t cbcr_src_w = src_w; + uint16_t cbcr_src_h = src_h; u8 gt2 = 0; u8 gt4 = 0; u32 val; @@ -763,27 +765,27 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); if (info->is_yuv) { - src_w /= info->hsub; - src_h /= info->vsub; + cbcr_src_w /= info->hsub; + cbcr_src_h /= info->vsub; gt4 = 0; gt2 = 0; - if (src_h >= (4 * dst_h)) { + if (cbcr_src_h >= (4 * dst_h)) { gt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { + cbcr_src_h >>= 2; + } else if (cbcr_src_h >= (2 * dst_h)) { gt2 = 1; - src_h >>= 1; + cbcr_src_h >>= 1; } - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); + hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); + ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); - val = vop2_scale_factor(src_w, dst_w); + val = vop2_scale_factor(cbcr_src_w, dst_w); vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); - val = vop2_scale_factor(src_h, dst_h); + val = vop2_scale_factor(cbcr_src_h, dst_h); vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
For the cbcr format, gt2 and gt4 are computed again after src_h has been divided by vsub. As src_h as already been divided by 2 before, introduce cbcr_src_h and cbcr_src_w to keep a copy of those values to be used for cbcr gt2 and gt4 computation. This fixes yuv planes being unaligned vertically when down scaling to 1080 pixels from 2160. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 22 +++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-)