Message ID | 20240417114231.7044-1-marex@denx.de (mailing list archive) |
---|---|
State | In Next, archived |
Headers | show |
Series | [v3] arm64: dts: imx8mp: Align both CSI2 pixel clock | expand |
On 17.04.24 13:42, Marek Vasut wrote: > Configure both CSI2 clock-frequency and assigned-clock-rates > the same way. There does not seem to be any reason for keeping > the two CSI2 pixel clock set to different frequencies. > > This also reduces first CSI2 clock from overdrive mode > frequency which is 500 MHz down below the regular mode > frequency of 400 MHz. > > Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Thanks, Ahmad > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Cc: Paul Elder <paul.elder@ideasonboard.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > V2: Align both clock to 266 MHz and update commit message > V3: - Fix up clock-frequency to 266 MHz as well, update commit message > - Add RB from Peng and Alexander, but maybe those need to be updated? > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 1bb96e96639f2..b92abb5a5c536 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1657,7 +1657,7 @@ mipi_csi_0: csi@32e40000 { > compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; > reg = <0x32e40000 0x10000>; > interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > - clock-frequency = <500000000>; > + clock-frequency = <266000000>; > clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, > <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, > @@ -1667,7 +1667,7 @@ mipi_csi_0: csi@32e40000 { > <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > <&clk IMX8MP_CLK_24M>; > - assigned-clock-rates = <500000000>; > + assigned-clock-rates = <266000000>; > power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; > status = "disabled"; >
On Wed, Apr 17, 2024 at 01:42:06PM +0200, Marek Vasut wrote: > Configure both CSI2 clock-frequency and assigned-clock-rates > the same way. There does not seem to be any reason for keeping > the two CSI2 pixel clock set to different frequencies. > > This also reduces first CSI2 clock from overdrive mode > frequency which is 500 MHz down below the regular mode > frequency of 400 MHz. > > Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Marek Vasut <marex@denx.de> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 1bb96e96639f2..b92abb5a5c536 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1657,7 +1657,7 @@ mipi_csi_0: csi@32e40000 { compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <500000000>; + clock-frequency = <266000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1667,7 +1667,7 @@ mipi_csi_0: csi@32e40000 { <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <500000000>; + assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled";