| Message ID | 20240422101905.32703-2-andyshrk@163.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix the port mux of VP2 | expand |
On Mon, Apr 22, 2024 at 06:19:05PM +0800, Andy Yan wrote: > From: Andy Yan <andy.yan@rock-chips.com> > > The port mux of VP2 should be RK3568_OVL_PORT_SET__PORT2_MUX. > > Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha > > --- > > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > index 97b0ab4b6db8..1f4250de570f 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > @@ -2377,7 +2377,7 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) > port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, > (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); > else > - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); > + port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 8); > > layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); > > -- > 2.34.1 > >
Am Montag, 22. April 2024, 12:19:05 CEST schrieb Andy Yan: > From: Andy Yan <andy.yan@rock-chips.com> > > The port mux of VP2 should be RK3568_OVL_PORT_SET__PORT2_MUX. > > Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> on a rk3588 with VP3 connected to a DSI display Tested-by: Heiko Stuebner <heiko@sntech.de>
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 97b0ab4b6db8..1f4250de570f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2377,7 +2377,7 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); + port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 8); layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);