diff mbox series

[v3,07/10] arm64: dts: imx8qm-mek: add flexcan support

Message ID 20240422-dts_8qm_audio-v3-7-680cee731ced@nxp.com (mailing list archive)
State Superseded
Headers show
Series arm64: dts: imx8qm Add audio\flexcan\i2c\fec1 nodes for imx8qm-mek board | expand

Commit Message

Frank Li April 22, 2024, 7:50 p.m. UTC 
Add flexcan[1,2,3] support for imx8qm-mek board.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 80 ++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

Comments

Marc Kleine-Budde April 23, 2024, 7:53 a.m. UTC | #1 
On 22.04.2024 15:50:09, Frank Li wrote:
> Add flexcan[1,2,3] support for imx8qm-mek board.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 80 ++++++++++++++++++++++++++++
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 3ab2fab7f7fa3..62ea3efd1ee2c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
[...]
> @@ -433,6 +492,27 @@ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
>  		>;
>  	};
>  
> +	pinctrl_flexcan1: flexcan0grp {
> +		fsl,pins = <
> +			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21
> +			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x21
> +		>;
> +	};
> +
> +	pinctrl_flexcan2: flexcan1grp {
> +		fsl,pins = <
> +			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x21
> +			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x21
> +			>;

The indention of the closing ">" looks strange.

> +	};
> +
> +	pinctrl_flexcan3: flexcan3grp {
> +		fsl,pins = <
> +			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x21
> +			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x21
> +			>;

Same here.

> +	};
> +
>  	pinctrl_lpuart0: lpuart0grp {
>  		fsl,pins = <
>  			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
> 
> -- 
> 2.34.1
> 
> 
>

regards,
Marc
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 3ab2fab7f7fa3..62ea3efd1ee2c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -40,6 +40,44 @@  reg_usdhc2_vmmc: usdhc2-vmmc {
 		enable-active-high;
 	};
 
+	reg_can01_en: regulator-can01-gen {
+		compatible = "regulator-fixed";
+		regulator-name = "can01-en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_can2_en: regulator-can2-gen {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_can01_stby: regulator-can01-stby {
+		compatible = "regulator-fixed";
+		regulator-name = "can01-stby";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_can01_en>;
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-stby";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_can2_en>;
+	};
+
 	reg_vref_1v8: regulator-adc-vref {
 		compatible = "regulator-fixed";
 		regulator-name = "vref_1v8";
@@ -241,6 +279,27 @@  &cm41_intmux {
 	status = "okay";
 };
 
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can01_stby>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can01_stby>;
+	status = "okay";
+};
+
+&flexcan3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan3>;
+	xceiver-supply = <&reg_can2_stby>;
+	status = "okay";
+};
+
 &lpuart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
@@ -433,6 +492,27 @@  IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
 		>;
 	};
 
+	pinctrl_flexcan1: flexcan0grp {
+		fsl,pins = <
+			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21
+			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x21
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan1grp {
+		fsl,pins = <
+			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x21
+			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x21
+			>;
+	};
+
+	pinctrl_flexcan3: flexcan3grp {
+		fsl,pins = <
+			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x21
+			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x21
+			>;
+	};
+
 	pinctrl_lpuart0: lpuart0grp {
 		fsl,pins = <
 			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020