Message ID | 20240403154844.3403859-2-dave.jiang@intel.com |
---|---|
State | Accepted |
Commit | 648dae58a830ecceea3b1bebf68432435980f137 |
Headers | show |
Series | cxl: access_coordinate validity fixes for 6.9 | expand |
On 03.04.24 08:47:12, Dave Jiang wrote: > The while() loop in cxl_endpoint_get_perf_coordinates() checks to see if > 'iter' is valid as part of the condition breaking out of the loop. > is_cxl_root() will stop the loop before the next iteration could go NULL. > Remove the iter check. > > The presence of the iter or removing the iter does not impact the behavior > of the code. This is a code clean up and not a bug fix. > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/core/port.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 2b0cab556072..6cbde50a742b 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -2197,7 +2197,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, > * port each iteration. If the parent is cxl root then there is > * nothing to gather. > */ > - while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { > + while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { I am seeing the following mainline after [1]: [ 39.815379] cxl_acpi ACPI0017:00: not a cxl_port device [ 39.827123] WARNING: CPU: 46 PID: 1754 at drivers/cxl/core/port.c:592 to_cxl_port+0x56/0x70 [cxl_core] ... plus some related subsequent NULL pointer dereference: [ 40.718708] BUG: kernel NULL pointer dereference, address: 00000000000002d8 This changes looks related. I am going to dig deeper here but just a headsup in advance. Note this is tested on an RCH topology. Thanks, -Robert [1] commit 586b5dfb51b9 ("Merge tag 'cxl-fixes-6.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl"): > cxl_coordinates_combine(&c, &c, &dport->sw_coord); > c.write_latency += dport->link_latency; > c.read_latency += dport->link_latency; > -- > 2.44.0 >
On 4/26/24 12:10 PM, Robert Richter wrote: > On 03.04.24 08:47:12, Dave Jiang wrote: >> The while() loop in cxl_endpoint_get_perf_coordinates() checks to see if >> 'iter' is valid as part of the condition breaking out of the loop. >> is_cxl_root() will stop the loop before the next iteration could go NULL. >> Remove the iter check. >> >> The presence of the iter or removing the iter does not impact the behavior >> of the code. This is a code clean up and not a bug fix. >> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> >> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> >> Reviewed-by: Dan Williams <dan.j.williams@intel.com> >> Signed-off-by: Dave Jiang <dave.jiang@intel.com> >> --- >> drivers/cxl/core/port.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c >> index 2b0cab556072..6cbde50a742b 100644 >> --- a/drivers/cxl/core/port.c >> +++ b/drivers/cxl/core/port.c >> @@ -2197,7 +2197,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, >> * port each iteration. If the parent is cxl root then there is >> * nothing to gather. >> */ >> - while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { >> + while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { > > I am seeing the following mainline after [1]: > > [ 39.815379] cxl_acpi ACPI0017:00: not a cxl_port device > [ 39.827123] WARNING: CPU: 46 PID: 1754 at drivers/cxl/core/port.c:592 to_cxl_port+0x56/0x70 [cxl_core] > > ... plus some related subsequent NULL pointer dereference: > > [ 40.718708] BUG: kernel NULL pointer dereference, address: 00000000000002d8 > > This changes looks related. I am going to dig deeper here but just a > headsup in advance. > > Note this is tested on an RCH topology. Hi Robert, Can you please provide the 'ls -l /sys/bus/cxl/devices/$memX' of the RCH device? Maybe the iterator may need to be tweaked for RCH topology support. > > Thanks, > > -Robert > > [1] commit 586b5dfb51b9 ("Merge tag 'cxl-fixes-6.9-rc4' of > git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl"): > >> cxl_coordinates_combine(&c, &c, &dport->sw_coord); >> c.write_latency += dport->link_latency; >> c.read_latency += dport->link_latency; >> -- >> 2.44.0 >> >
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2b0cab556072..6cbde50a742b 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2197,7 +2197,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, * port each iteration. If the parent is cxl root then there is * nothing to gather. */ - while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { + while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { cxl_coordinates_combine(&c, &c, &dport->sw_coord); c.write_latency += dport->link_latency; c.read_latency += dport->link_latency;