| Message ID | 20240425171311.19519-3-ricardo.neri-calderon@linux.intel.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | drivers: thermal/hwmon: intel: Use model-specific bitmasks for temperature registers | expand |
On Thu, 2024-04-25 at 10:13 -0700, Ricardo Neri wrote: > The TCC offset field in the register MSR_TEMPERATURE_TARGET is not > architectural. The TCC library provides a model-specific bitmask. Use > it to > determine the maximum TCC offset. > > Suggested-by: Zhang Rui <rui.zhang@intel.com> > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> -rui > --- > Cc: Daniel Lezcano <daniel.lezcano@linaro.org> > Cc: Lukasz Luba <lukasz.luba@arm.com> > Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> > Cc: linux-hwmon@vger.kernel.org > Cc: linux-pm@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: stable@vger.kernel.org # v6.7+ > --- > Changes since v1: > * Used renamed function intel_tcc_get_offset_mask(). > --- > drivers/thermal/intel/intel_tcc_cooling.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/thermal/intel/intel_tcc_cooling.c > b/drivers/thermal/intel/intel_tcc_cooling.c > index 6c392147e6d1..5bfc2b515c78 100644 > --- a/drivers/thermal/intel/intel_tcc_cooling.c > +++ b/drivers/thermal/intel/intel_tcc_cooling.c > @@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev; > static int tcc_get_max_state(struct thermal_cooling_device *cdev, > unsigned long > *state) > { > - *state = 0x3f; > + *state = intel_tcc_get_offset_mask(); > return 0; > } >
diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 6c392147e6d1..5bfc2b515c78 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = 0x3f; + *state = intel_tcc_get_offset_mask(); return 0; }
The TCC offset field in the register MSR_TEMPERATURE_TARGET is not architectural. The TCC library provides a model-specific bitmask. Use it to determine the maximum TCC offset. Suggested-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> --- Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Lukasz Luba <lukasz.luba@arm.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- Changes since v1: * Used renamed function intel_tcc_get_offset_mask(). --- drivers/thermal/intel/intel_tcc_cooling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)