Message ID | 20240307160319.675044-6-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | riscv: QEMU RISC-V IOMMU Support | expand |
Reviewed-by: Frank Chang <frank.chang@sifive.com> Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年3月8日 週五 上午12:05寫道: > > From: Tomasz Jeznach <tjeznach@rivosinc.com> > > This device models the RISC-V IOMMU as a sysbus device. > > Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > hw/riscv/meson.build | 2 +- > hw/riscv/riscv-iommu-sys.c | 93 ++++++++++++++++++++++++++++++++++++++ > include/hw/riscv/iommu.h | 4 ++ > 3 files changed, 98 insertions(+), 1 deletion(-) > create mode 100644 hw/riscv/riscv-iommu-sys.c > > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index 4674cec6c4..e37c5d78e2 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) > riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) > riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) > riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) > -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) > +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c')) > > hw_arch += {'riscv': riscv_ss} > diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c > new file mode 100644 > index 0000000000..4305cf8d79 > --- /dev/null > +++ b/hw/riscv/riscv-iommu-sys.c > @@ -0,0 +1,93 @@ > +/* > + * QEMU emulation of an RISC-V IOMMU (Ziommu) - Platform Device > + * > + * Copyright (C) 2022-2023 Rivos Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/pci/pci_bus.h" > +#include "hw/qdev-properties.h" > +#include "hw/sysbus.h" > +#include "qapi/error.h" > +#include "qapi/error.h" > +#include "qemu/error-report.h" > +#include "qemu/host-utils.h" > +#include "qemu/module.h" > +#include "qemu/osdep.h" > +#include "qom/object.h" > + > +#include "riscv-iommu.h" > + > +/* RISC-V IOMMU System Platform Device Emulation */ > + > +struct RISCVIOMMUStateSys { > + SysBusDevice parent; > + uint64_t addr; > + RISCVIOMMUState iommu; > +}; > + > +static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) > +{ > + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); > + PCIBus *pci_bus; > + > + qdev_realize(DEVICE(&s->iommu), NULL, errp); > + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); > + if (s->addr) { > + sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); > + } > + > + pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); > + if (pci_bus) { > + riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); > + } > +} > + > +static void riscv_iommu_sys_init(Object *obj) > +{ > + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); > + RISCVIOMMUState *iommu = &s->iommu; > + > + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); > + qdev_alias_all_properties(DEVICE(iommu), obj); > +} > + > +static Property riscv_iommu_sys_properties[] = { > + DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + dc->realize = riscv_iommu_sys_realize; > + set_bit(DEVICE_CATEGORY_MISC, dc->categories); > + device_class_set_props(dc, riscv_iommu_sys_properties); > +} > + > +static const TypeInfo riscv_iommu_sys = { > + .name = TYPE_RISCV_IOMMU_SYS, > + .parent = TYPE_SYS_BUS_DEVICE, > + .class_init = riscv_iommu_sys_class_init, > + .instance_init = riscv_iommu_sys_init, > + .instance_size = sizeof(RISCVIOMMUStateSys), > +}; > + > +static void riscv_iommu_register_sys(void) > +{ > + type_register_static(&riscv_iommu_sys); > +} > + > +type_init(riscv_iommu_register_sys) > diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h > index 403b365893..c8d28a79a1 100644 > --- a/include/hw/riscv/iommu.h > +++ b/include/hw/riscv/iommu.h > @@ -33,4 +33,8 @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; > OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) > typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; > > +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" > +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) > +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; > + > #endif > -- > 2.43.2 > >
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 4674cec6c4..e37c5d78e2 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c')) hw_arch += {'riscv': riscv_ss} diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c new file mode 100644 index 0000000000..4305cf8d79 --- /dev/null +++ b/hw/riscv/riscv-iommu-sys.c @@ -0,0 +1,93 @@ +/* + * QEMU emulation of an RISC-V IOMMU (Ziommu) - Platform Device + * + * Copyright (C) 2022-2023 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci_bus.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qapi/error.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/host-utils.h" +#include "qemu/module.h" +#include "qemu/osdep.h" +#include "qom/object.h" + +#include "riscv-iommu.h" + +/* RISC-V IOMMU System Platform Device Emulation */ + +struct RISCVIOMMUStateSys { + SysBusDevice parent; + uint64_t addr; + RISCVIOMMUState iommu; +}; + +static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) +{ + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); + PCIBus *pci_bus; + + qdev_realize(DEVICE(&s->iommu), NULL, errp); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); + if (s->addr) { + sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); + } + + pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); + if (pci_bus) { + riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); + } +} + +static void riscv_iommu_sys_init(Object *obj) +{ + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); + RISCVIOMMUState *iommu = &s->iommu; + + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); + qdev_alias_all_properties(DEVICE(iommu), obj); +} + +static Property riscv_iommu_sys_properties[] = { + DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = riscv_iommu_sys_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + device_class_set_props(dc, riscv_iommu_sys_properties); +} + +static const TypeInfo riscv_iommu_sys = { + .name = TYPE_RISCV_IOMMU_SYS, + .parent = TYPE_SYS_BUS_DEVICE, + .class_init = riscv_iommu_sys_class_init, + .instance_init = riscv_iommu_sys_init, + .instance_size = sizeof(RISCVIOMMUStateSys), +}; + +static void riscv_iommu_register_sys(void) +{ + type_register_static(&riscv_iommu_sys); +} + +type_init(riscv_iommu_register_sys) diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index 403b365893..c8d28a79a1 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -33,4 +33,8 @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; + #endif