| Message ID | 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-1-868b15a17a45@linaro.org |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock | expand |
On Mon, Apr 22, 2024 at 06:16:18PM GMT, Neil Armstrong wrote: > Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy > provided QMP_PCIE_PHY_AUX_CLK. > This looks applicable to the other two patches, but I don't see the pcie-1-phy-aux-clk being removed in this patch. Furthermore, the cover letter does not make it into the git history, which results in rather lacking documentation on the reasoning for the change. Can you please update the three commit messages? Regards, Bjorn > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 616461fcbab9..71797f337d19 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&sleep_clk>, > <&pcie0_phy>, > - <&pcie1_phy>, > - <0>, > + <&pcie1_phy QMP_PCIE_PIPE_CLK>, > + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, > <&ufs_mem_phy 0>, > <&ufs_mem_phy 1>, > <&ufs_mem_phy 2>, > @@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 { > "rchng", > "pipe"; > > - clock-output-names = "pcie_1_pipe_clk"; > - #clock-cells = <0>; > + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; > + #clock-cells = <1>; > > #phy-cells = <0>; > > > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 616461fcbab9..71797f337d19 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 { "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells = <1>; #phy-cells = <0>;