| Message ID | 20240429120755.3990652-2-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Panel replay selective update support | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Monday, April 29, 2024 5:38 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > <jouni.hogander@intel.com> > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > has_sel_update > > We are going to reuse has_psr2 for panel_replay as well. Rename it as > has_sel_update to avoid confusion. > > v2: Rebase > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +++++----- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- > 6 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > index ccaa4cb2809b..2c391714f28e 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > intel_crtc_state *pipe_config, > drm_printf(&p, "sdp split: %s\n", > str_enabled_disabled(pipe_config- > >sdp_split_enable)); > > - drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective > fetch: %s\n", > - str_enabled_disabled(pipe_config->has_psr), > - str_enabled_disabled(pipe_config->has_psr2), > - str_enabled_disabled(pipe_config- > >has_panel_replay), > - str_enabled_disabled(pipe_config- > >enable_psr2_sel_fetch)); > + drm_printf(&p, "psr: %s, selective update: %s, panel replay: > %s, selective fetch: %s\n", > + str_enabled_disabled(pipe_config->has_psr), > + str_enabled_disabled(pipe_config- > >has_sel_update), > + str_enabled_disabled(pipe_config- > >has_panel_replay), > + str_enabled_disabled(pipe_config- > >enable_psr2_sel_fetch)); During panel-replay has_psr flag also will be true. So will get print as psr enabled. Something below may give correct info, if (pipe_config->has_panel_replay) drm_printf(&p, "psr: disabled, panel replay: enabled"); else drm_printf(&p, "psr: %s, panel replay: disabled", str_enabled_disabled(pipe_config->has_psr)); drm_printf(&p, "selective update: %s, selective fetch: %s\n", str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); Regards, Animesh > } > > drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", diff > --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index f45e5f02096d..c1aba4e8ac54 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct > intel_crtc_state *current_config, > */ > if (current_config->has_panel_replay || pipe_config- > >has_panel_replay) { > PIPE_CONF_CHECK_BOOL(has_psr); > - PIPE_CONF_CHECK_BOOL(has_psr2); > + PIPE_CONF_CHECK_BOOL(has_sel_update); > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); > PIPE_CONF_CHECK_BOOL(has_panel_replay); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 62f7a30c37dc..6747c10da298 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1189,7 +1189,7 @@ struct intel_crtc_state { > > /* PSR is supported but might not be enabled due the lack of enabled > planes */ > bool has_psr; > - bool has_psr2; > + bool has_sel_update; > bool enable_psr2_sel_fetch; > bool enable_psr2_su_region_et; > bool req_psr2_sdp_prior_scanline; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index e05e25cd4a94..a7c406a9695f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct > intel_dp *intel_dp, > if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, > vsc); > - } else if (crtc_state->has_psr2) { > + } else if (crtc_state->has_psr && crtc_state->has_sel_update) { > /* > * [PSR2 without colorimetry] > * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index 151dcd0c45b6..984f13d8c0c8 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct > intel_atomic_state *state, > * Recommendation is to keep this combination disabled > * Bspec: 50422 HSD: 14010260002 > */ > - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { > + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { > plane_state->no_fbc_reason = "PSR2 enabled"; > return 0; > } > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index f5b33335a9ae..a2f7d998d342 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > u8 dpcd_val = DP_PSR_ENABLE; > > - if (crtc_state->has_psr2) { > + if (crtc_state->has_sel_update) { > /* Enable ALPM at sink for psr2 */ > if (!crtc_state->has_panel_replay) { > drm_dp_dpcd_writeb(&intel_dp->aux, > @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > if (!crtc_state->has_psr) > return; > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > + crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, > +crtc_state); > } > > void intel_psr_get_config(struct intel_encoder *encoder, @@ -1672,7 > +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, > pipe_config->has_psr = true; > } > > - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; > + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; > pipe_config->infoframes.enable |= > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > if (!intel_dp->psr.psr2_enabled) > @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct intel_dp > *intel_dp, > > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; > intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; > intel_dp->psr.busy_frontbuffer_bits = 0; > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; > @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct > intel_atomic_state *state, > needs_to_disable |= > intel_crtc_needs_modeset(new_crtc_state); > needs_to_disable |= !new_crtc_state->has_psr; > needs_to_disable |= !new_crtc_state->active_planes; > - needs_to_disable |= new_crtc_state->has_psr2 != psr- > >psr2_enabled; > + needs_to_disable |= new_crtc_state->has_sel_update != > +psr->psr2_enabled; > needs_to_disable |= DISPLAY_VER(i915) < 11 && > new_crtc_state->wm_level_disabled; > > -- > 2.34.1
> -----Original Message----- > From: Manna, Animesh > Sent: Tuesday, April 30, 2024 12:24 AM > To: Hogander, Jouni <jouni.hogander@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > has_sel_update > > > > > -----Original Message----- > > From: Hogander, Jouni <jouni.hogander@intel.com> > > Sent: Monday, April 29, 2024 5:38 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > > <jouni.hogander@intel.com> > > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > has_sel_update > > > > We are going to reuse has_psr2 for panel_replay as well. Rename it as > > has_sel_update to avoid confusion. > > > > v2: Rebase > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +++++----- > > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- > > 6 files changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > index ccaa4cb2809b..2c391714f28e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > > intel_crtc_state *pipe_config, > > drm_printf(&p, "sdp split: %s\n", > > str_enabled_disabled(pipe_config- > > >sdp_split_enable)); > > > > - drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective > > fetch: %s\n", > > - str_enabled_disabled(pipe_config->has_psr), > > - str_enabled_disabled(pipe_config->has_psr2), > > - str_enabled_disabled(pipe_config- > > >has_panel_replay), > > - str_enabled_disabled(pipe_config- > > >enable_psr2_sel_fetch)); > > + drm_printf(&p, "psr: %s, selective update: %s, panel replay: > > %s, selective fetch: %s\n", > > + str_enabled_disabled(pipe_config->has_psr), > > + str_enabled_disabled(pipe_config- > > >has_sel_update), > > + str_enabled_disabled(pipe_config- > > >has_panel_replay), > > + str_enabled_disabled(pipe_config- > > >enable_psr2_sel_fetch)); > > During panel-replay has_psr flag also will be true. So will get print as psr > enabled. > Something below may give correct info, > if (pipe_config->has_panel_replay) > drm_printf(&p, "psr: disabled, panel replay: enabled"); > else > drm_printf(&p, "psr: %s, panel replay: disabled", > str_enabled_disabled(pipe_config->has_psr)); > > drm_printf(&p, "selective update: %s, selective fetch: %s\n", > str_enabled_disabled(pipe_config->has_sel_update), > str_enabled_disabled(pipe_config- > >enable_psr2_sel_fetch)); > > Regards, > Animesh > > > } > > > > drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", diff > > --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index f45e5f02096d..c1aba4e8ac54 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct > > intel_crtc_state *current_config, > > */ > > if (current_config->has_panel_replay || pipe_config- > > >has_panel_replay) { > > PIPE_CONF_CHECK_BOOL(has_psr); > > - PIPE_CONF_CHECK_BOOL(has_psr2); > > + PIPE_CONF_CHECK_BOOL(has_sel_update); > > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); > > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); > > PIPE_CONF_CHECK_BOOL(has_panel_replay); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 62f7a30c37dc..6747c10da298 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1189,7 +1189,7 @@ struct intel_crtc_state { > > > > /* PSR is supported but might not be enabled due the lack of enabled > > planes */ > > bool has_psr; > > - bool has_psr2; > > + bool has_sel_update; > > bool enable_psr2_sel_fetch; > > bool enable_psr2_su_region_et; > > bool req_psr2_sdp_prior_scanline; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index e05e25cd4a94..a7c406a9695f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct > > intel_dp *intel_dp, > > if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > > intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, > > vsc); > > - } else if (crtc_state->has_psr2) { > > + } else if (crtc_state->has_psr && crtc_state->has_sel_update) { has_psr check may not be needed if patch2 of this series is placed at 1st position. Regards, Animesh > > /* > > * [PSR2 without colorimetry] > > * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 > diff > > --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > index 151dcd0c45b6..984f13d8c0c8 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct > > intel_atomic_state *state, > > * Recommendation is to keep this combination disabled > > * Bspec: 50422 HSD: 14010260002 > > */ > > - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { > > + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { > > plane_state->no_fbc_reason = "PSR2 enabled"; > > return 0; > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index f5b33335a9ae..a2f7d998d342 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > u8 dpcd_val = DP_PSR_ENABLE; > > > > - if (crtc_state->has_psr2) { > > + if (crtc_state->has_sel_update) { > > /* Enable ALPM at sink for psr2 */ > > if (!crtc_state->has_panel_replay) { > > drm_dp_dpcd_writeb(&intel_dp->aux, > > @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > if (!crtc_state->has_psr) > > return; > > > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > > + crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, > > +crtc_state); > > } > > > > void intel_psr_get_config(struct intel_encoder *encoder, @@ -1672,7 > > +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, > > pipe_config->has_psr = true; > > } > > > > - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; > > + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; > > pipe_config->infoframes.enable |= > > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > > > if (!intel_dp->psr.psr2_enabled) > > @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct > > intel_dp *intel_dp, > > > > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > > > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > > + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; > > intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; > > intel_dp->psr.busy_frontbuffer_bits = 0; > > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; > > @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct > > intel_atomic_state *state, > > needs_to_disable |= > > intel_crtc_needs_modeset(new_crtc_state); > > needs_to_disable |= !new_crtc_state->has_psr; > > needs_to_disable |= !new_crtc_state->active_planes; > > - needs_to_disable |= new_crtc_state->has_psr2 != psr- > > >psr2_enabled; > > + needs_to_disable |= new_crtc_state->has_sel_update != > > +psr->psr2_enabled; > > needs_to_disable |= DISPLAY_VER(i915) < 11 && > > new_crtc_state->wm_level_disabled; > > > > -- > > 2.34.1
On Mon, 2024-04-29 at 18:54 +0000, Manna, Animesh wrote: > > > > -----Original Message----- > > From: Hogander, Jouni <jouni.hogander@intel.com> > > Sent: Monday, April 29, 2024 5:38 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > > <jouni.hogander@intel.com> > > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > has_sel_update > > > > We are going to reuse has_psr2 for panel_replay as well. Rename it > > as > > has_sel_update to avoid confusion. > > > > v2: Rebase > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +++++--- > > -- > > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++--- > > -- > > 6 files changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > index ccaa4cb2809b..2c391714f28e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > > intel_crtc_state *pipe_config, > > drm_printf(&p, "sdp split: %s\n", > > str_enabled_disabled(pipe_config- > > > sdp_split_enable)); > > > > - drm_printf(&p, "psr: %s, psr2: %s, panel replay: > > %s, selective > > fetch: %s\n", > > - str_enabled_disabled(pipe_config- > > >has_psr), > > - str_enabled_disabled(pipe_config- > > >has_psr2), > > - str_enabled_disabled(pipe_config- > > > has_panel_replay), > > - str_enabled_disabled(pipe_config- > > > enable_psr2_sel_fetch)); > > + drm_printf(&p, "psr: %s, selective update: %s, > > panel replay: > > %s, selective fetch: %s\n", > > + str_enabled_disabled(pipe_config- > > >has_psr), > > + str_enabled_disabled(pipe_config- > > > has_sel_update), > > + str_enabled_disabled(pipe_config- > > > has_panel_replay), > > + str_enabled_disabled(pipe_config- > > > enable_psr2_sel_fetch)); > > During panel-replay has_psr flag also will be true. So will get print > as psr enabled. > Something below may give correct info, > if (pipe_config->has_panel_replay) > drm_printf(&p, "psr: disabled, panel replay: > enabled"); > else > drm_printf(&p, "psr: %s, panel replay: > disabled", > > str_enabled_disabled(pipe_config->has_psr)); > > drm_printf(&p, "selective update: %s, selective > fetch: %s\n", > > str_enabled_disabled(pipe_config->has_sel_update), > > str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); This is actually not in scope of this patch. Would you mind if we change this in separate patch not in this set? BR, Jouni Högander > > Regards, > Animesh > > > } > > > > drm_printf(&p, "framestart delay: %d, MSA timing delay: > > %d\n", diff > > --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index f45e5f02096d..c1aba4e8ac54 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct > > intel_crtc_state *current_config, > > */ > > if (current_config->has_panel_replay || pipe_config- > > > has_panel_replay) { > > PIPE_CONF_CHECK_BOOL(has_psr); > > - PIPE_CONF_CHECK_BOOL(has_psr2); > > + PIPE_CONF_CHECK_BOOL(has_sel_update); > > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); > > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); > > PIPE_CONF_CHECK_BOOL(has_panel_replay); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 62f7a30c37dc..6747c10da298 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1189,7 +1189,7 @@ struct intel_crtc_state { > > > > /* PSR is supported but might not be enabled due the lack > > of enabled > > planes */ > > bool has_psr; > > - bool has_psr2; > > + bool has_sel_update; > > bool enable_psr2_sel_fetch; > > bool enable_psr2_su_region_et; > > bool req_psr2_sdp_prior_scanline; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index e05e25cd4a94..a7c406a9695f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct > > intel_dp *intel_dp, > > if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > > intel_dp_compute_vsc_colorimetry(crtc_state, > > conn_state, > > vsc); > > - } else if (crtc_state->has_psr2) { > > + } else if (crtc_state->has_psr && crtc_state- > > >has_sel_update) { > > /* > > * [PSR2 without colorimetry] > > * Prepare VSC Header for SU as per eDP 1.4 spec, > > Table 6-11 > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > index 151dcd0c45b6..984f13d8c0c8 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct > > intel_atomic_state *state, > > * Recommendation is to keep this combination disabled > > * Bspec: 50422 HSD: 14010260002 > > */ > > - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { > > + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state- > > >has_sel_update) { > > plane_state->no_fbc_reason = "PSR2 enabled"; > > return 0; > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index f5b33335a9ae..a2f7d998d342 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp > > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > u8 dpcd_val = DP_PSR_ENABLE; > > > > - if (crtc_state->has_psr2) { > > + if (crtc_state->has_sel_update) { > > /* Enable ALPM at sink for psr2 */ > > if (!crtc_state->has_panel_replay) { > > drm_dp_dpcd_writeb(&intel_dp->aux, > > @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > if (!crtc_state->has_psr) > > return; > > > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, > > crtc_state); > > + crtc_state->has_sel_update = > > intel_psr2_config_valid(intel_dp, > > +crtc_state); > > } > > > > void intel_psr_get_config(struct intel_encoder *encoder, @@ - > > 1672,7 > > +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, > > pipe_config->has_psr = true; > > } > > > > - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; > > + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; > > pipe_config->infoframes.enable |= > > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > > > if (!intel_dp->psr.psr2_enabled) > > @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct > > intel_dp > > *intel_dp, > > > > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > > > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > > + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; > > intel_dp->psr.panel_replay_enabled = crtc_state- > > >has_panel_replay; > > intel_dp->psr.busy_frontbuffer_bits = 0; > > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)- > > >pipe; > > @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct > > intel_atomic_state *state, > > needs_to_disable |= > > intel_crtc_needs_modeset(new_crtc_state); > > needs_to_disable |= !new_crtc_state->has_psr; > > needs_to_disable |= !new_crtc_state->active_planes; > > - needs_to_disable |= new_crtc_state->has_psr2 != > > psr- > > > psr2_enabled; > > + needs_to_disable |= new_crtc_state->has_sel_update > > != > > +psr->psr2_enabled; > > needs_to_disable |= DISPLAY_VER(i915) < 11 && > > new_crtc_state->wm_level_disabled; > > > > -- > > 2.34.1 >
On Mon, 2024-04-29 at 19:08 +0000, Manna, Animesh wrote: > > > > -----Original Message----- > > From: Manna, Animesh > > Sent: Tuesday, April 30, 2024 12:24 AM > > To: Hogander, Jouni <jouni.hogander@intel.com>; intel- > > gfx@lists.freedesktop.org > > Subject: RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > has_sel_update > > > > > > > > > -----Original Message----- > > > From: Hogander, Jouni <jouni.hogander@intel.com> > > > Sent: Monday, April 29, 2024 5:38 PM > > > To: intel-gfx@lists.freedesktop.org > > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > > > <jouni.hogander@intel.com> > > > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > > has_sel_update > > > > > > We are going to reuse has_psr2 for panel_replay as well. Rename > > > it as > > > has_sel_update to avoid confusion. > > > > > > v2: Rebase > > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +++++- > > > ---- > > > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++- > > > ---- > > > 6 files changed, 14 insertions(+), 14 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > index ccaa4cb2809b..2c391714f28e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > > > intel_crtc_state *pipe_config, > > > drm_printf(&p, "sdp split: %s\n", > > > str_enabled_disabled(pipe_config- > > > > sdp_split_enable)); > > > > > > - drm_printf(&p, "psr: %s, psr2: %s, panel replay: > > > %s, selective > > > fetch: %s\n", > > > - str_enabled_disabled(pipe_config- > > > >has_psr), > > > - str_enabled_disabled(pipe_config- > > > >has_psr2), > > > - str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > - str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > + drm_printf(&p, "psr: %s, selective update: %s, > > > panel replay: > > > %s, selective fetch: %s\n", > > > + str_enabled_disabled(pipe_config- > > > >has_psr), > > > + str_enabled_disabled(pipe_config- > > > > has_sel_update), > > > + str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > + str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > > During panel-replay has_psr flag also will be true. So will get > > print as psr > > enabled. > > Something below may give correct info, > > if (pipe_config->has_panel_replay) > > drm_printf(&p, "psr: disabled, panel > > replay: enabled"); > > else > > drm_printf(&p, "psr: %s, panel replay: > > disabled", > > > > str_enabled_disabled(pipe_config->has_psr)); > > > > drm_printf(&p, "selective update: %s, selective > > fetch: %s\n", > > > > str_enabled_disabled(pipe_config->has_sel_update), > > > > str_enabled_disabled(pipe_config- > > > enable_psr2_sel_fetch)); > > > > Regards, > > Animesh > > > > > } > > > > > > drm_printf(&p, "framestart delay: %d, MSA timing delay: > > > %d\n", diff > > > --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index f45e5f02096d..c1aba4e8ac54 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct > > > intel_crtc_state *current_config, > > > */ > > > if (current_config->has_panel_replay || pipe_config- > > > > has_panel_replay) { > > > PIPE_CONF_CHECK_BOOL(has_psr); > > > - PIPE_CONF_CHECK_BOOL(has_psr2); > > > + PIPE_CONF_CHECK_BOOL(has_sel_update); > > > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); > > > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); > > > PIPE_CONF_CHECK_BOOL(has_panel_replay); > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 62f7a30c37dc..6747c10da298 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -1189,7 +1189,7 @@ struct intel_crtc_state { > > > > > > /* PSR is supported but might not be enabled due the lack > > > of enabled > > > planes */ > > > bool has_psr; > > > - bool has_psr2; > > > + bool has_sel_update; > > > bool enable_psr2_sel_fetch; > > > bool enable_psr2_su_region_et; > > > bool req_psr2_sdp_prior_scanline; > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index e05e25cd4a94..a7c406a9695f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct > > > intel_dp *intel_dp, > > > if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > > > intel_dp_compute_vsc_colorimetry(crtc_state, > > > conn_state, > > > vsc); > > > - } else if (crtc_state->has_psr2) { > > > + } else if (crtc_state->has_psr && crtc_state- > > > >has_sel_update) { > > has_psr check may not be needed if patch2 of this series is placed at > 1st position. I can drop has_psr check without order change as at this point selective update is not possible with Panel Replay. BR, Jouni Högander > > Regards, > Animesh > > > /* > > > * [PSR2 without colorimetry] > > > * Prepare VSC Header for SU as per eDP 1.4 spec, > > > Table 6-11 > > diff > > > --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index 151dcd0c45b6..984f13d8c0c8 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct > > > intel_atomic_state *state, > > > * Recommendation is to keep this combination disabled > > > * Bspec: 50422 HSD: 14010260002 > > > */ > > > - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) > > > { > > > + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state- > > > >has_sel_update) { > > > plane_state->no_fbc_reason = "PSR2 enabled"; > > > return 0; > > > } > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index f5b33335a9ae..a2f7d998d342 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp > > *intel_dp, > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > u8 dpcd_val = DP_PSR_ENABLE; > > > > > > - if (crtc_state->has_psr2) { > > > + if (crtc_state->has_sel_update) { > > > /* Enable ALPM at sink for psr2 */ > > > if (!crtc_state->has_panel_replay) { > > > drm_dp_dpcd_writeb(&intel_dp->aux, > > > @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct > > > intel_dp > > > *intel_dp, > > > if (!crtc_state->has_psr) > > > return; > > > > > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, > > > crtc_state); > > > + crtc_state->has_sel_update = > > > intel_psr2_config_valid(intel_dp, > > > +crtc_state); > > > } > > > > > > void intel_psr_get_config(struct intel_encoder *encoder, @@ - > > > 1672,7 > > > +1672,7 @@ void intel_psr_get_config(struct intel_encoder > > > *encoder, > > > pipe_config->has_psr = true; > > > } > > > > > > - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; > > > + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; > > > pipe_config->infoframes.enable |= > > > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > > > > > if (!intel_dp->psr.psr2_enabled) > > > @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct > > > intel_dp *intel_dp, > > > > > > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > > > > > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > > > + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; > > > intel_dp->psr.panel_replay_enabled = crtc_state- > > > >has_panel_replay; > > > intel_dp->psr.busy_frontbuffer_bits = 0; > > > intel_dp->psr.pipe = to_intel_crtc(crtc_state- > > > >uapi.crtc)->pipe; > > > @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct > > > intel_atomic_state *state, > > > needs_to_disable |= > > > intel_crtc_needs_modeset(new_crtc_state); > > > needs_to_disable |= !new_crtc_state->has_psr; > > > needs_to_disable |= !new_crtc_state- > > > >active_planes; > > > - needs_to_disable |= new_crtc_state->has_psr2 != > > > psr- > > > > psr2_enabled; > > > + needs_to_disable |= new_crtc_state- > > > >has_sel_update != > > > +psr->psr2_enabled; > > > needs_to_disable |= DISPLAY_VER(i915) < 11 && > > > new_crtc_state->wm_level_disabled; > > > > > > -- > > > 2.34.1 >
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Tuesday, April 30, 2024 11:52 AM > To: Manna, Animesh <animesh.manna@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > has_sel_update > > On Mon, 2024-04-29 at 18:54 +0000, Manna, Animesh wrote: > > > > > > > -----Original Message----- > > > From: Hogander, Jouni <jouni.hogander@intel.com> > > > Sent: Monday, April 29, 2024 5:38 PM > > > To: intel-gfx@lists.freedesktop.org > > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > > > <jouni.hogander@intel.com> > > > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > > has_sel_update > > > > > > We are going to reuse has_psr2 for panel_replay as well. Rename it > > > as > > > has_sel_update to avoid confusion. > > > > > > v2: Rebase > > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +++++--- > > > -- > > > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++--- > > > -- > > > 6 files changed, 14 insertions(+), 14 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > index ccaa4cb2809b..2c391714f28e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > > > intel_crtc_state *pipe_config, > > > drm_printf(&p, "sdp split: %s\n", > > > str_enabled_disabled(pipe_config- > > > > sdp_split_enable)); > > > > > > - drm_printf(&p, "psr: %s, psr2: %s, panel replay: > > > %s, selective > > > fetch: %s\n", > > > - str_enabled_disabled(pipe_config- > > > >has_psr), > > > - str_enabled_disabled(pipe_config- > > > >has_psr2), > > > - str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > - str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > + drm_printf(&p, "psr: %s, selective update: %s, > > > panel replay: > > > %s, selective fetch: %s\n", > > > + str_enabled_disabled(pipe_config- > > > >has_psr), > > > + str_enabled_disabled(pipe_config- > > > > has_sel_update), > > > + str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > + str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > > During panel-replay has_psr flag also will be true. So will get print > > as psr enabled. > > Something below may give correct info, > > if (pipe_config->has_panel_replay) > > drm_printf(&p, "psr: disabled, panel replay: > > enabled"); > > else > > drm_printf(&p, "psr: %s, panel replay: > > disabled", > > > > str_enabled_disabled(pipe_config->has_psr)); > > > > drm_printf(&p, "selective update: %s, selective > > fetch: %s\n", > > > > str_enabled_disabled(pipe_config->has_sel_update), > > > > str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); > > This is actually not in scope of this patch. Would you mind if we > change this in separate patch not in this set? Yes a separate patch will be good, but need to add in same patch series to adhere to documentation of these psr/pr related flags. Regards, Animesh > > BR, > > Jouni Högander > > > > > > Regards, > > Animesh > > > > > } > > > > > > drm_printf(&p, "framestart delay: %d, MSA timing delay: > > > %d\n", diff > > > --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index f45e5f02096d..c1aba4e8ac54 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct > > > intel_crtc_state *current_config, > > > */ > > > if (current_config->has_panel_replay || pipe_config- > > > > has_panel_replay) { > > > PIPE_CONF_CHECK_BOOL(has_psr); > > > - PIPE_CONF_CHECK_BOOL(has_psr2); > > > + PIPE_CONF_CHECK_BOOL(has_sel_update); > > > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); > > > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); > > > PIPE_CONF_CHECK_BOOL(has_panel_replay); > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 62f7a30c37dc..6747c10da298 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -1189,7 +1189,7 @@ struct intel_crtc_state { > > > > > > /* PSR is supported but might not be enabled due the lack > > > of enabled > > > planes */ > > > bool has_psr; > > > - bool has_psr2; > > > + bool has_sel_update; > > > bool enable_psr2_sel_fetch; > > > bool enable_psr2_su_region_et; > > > bool req_psr2_sdp_prior_scanline; > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index e05e25cd4a94..a7c406a9695f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct > > > intel_dp *intel_dp, > > > if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > > > intel_dp_compute_vsc_colorimetry(crtc_state, > > > conn_state, > > > vsc); > > > - } else if (crtc_state->has_psr2) { > > > + } else if (crtc_state->has_psr && crtc_state- > > > >has_sel_update) { > > > /* > > > * [PSR2 without colorimetry] > > > * Prepare VSC Header for SU as per eDP 1.4 spec, > > > Table 6-11 > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index 151dcd0c45b6..984f13d8c0c8 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct > > > intel_atomic_state *state, > > > * Recommendation is to keep this combination disabled > > > * Bspec: 50422 HSD: 14010260002 > > > */ > > > - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { > > > + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state- > > > >has_sel_update) { > > > plane_state->no_fbc_reason = "PSR2 enabled"; > > > return 0; > > > } > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index f5b33335a9ae..a2f7d998d342 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp > > > *intel_dp, > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > u8 dpcd_val = DP_PSR_ENABLE; > > > > > > - if (crtc_state->has_psr2) { > > > + if (crtc_state->has_sel_update) { > > > /* Enable ALPM at sink for psr2 */ > > > if (!crtc_state->has_panel_replay) { > > > drm_dp_dpcd_writeb(&intel_dp->aux, > > > @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp > > > *intel_dp, > > > if (!crtc_state->has_psr) > > > return; > > > > > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, > > > crtc_state); > > > + crtc_state->has_sel_update = > > > intel_psr2_config_valid(intel_dp, > > > +crtc_state); > > > } > > > > > > void intel_psr_get_config(struct intel_encoder *encoder, @@ - > > > 1672,7 > > > +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, > > > pipe_config->has_psr = true; > > > } > > > > > > - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; > > > + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; > > > pipe_config->infoframes.enable |= > > > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > > > > > if (!intel_dp->psr.psr2_enabled) > > > @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct > > > intel_dp > > > *intel_dp, > > > > > > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > > > > > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > > > + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; > > > intel_dp->psr.panel_replay_enabled = crtc_state- > > > >has_panel_replay; > > > intel_dp->psr.busy_frontbuffer_bits = 0; > > > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)- > > > >pipe; > > > @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct > > > intel_atomic_state *state, > > > needs_to_disable |= > > > intel_crtc_needs_modeset(new_crtc_state); > > > needs_to_disable |= !new_crtc_state->has_psr; > > > needs_to_disable |= !new_crtc_state->active_planes; > > > - needs_to_disable |= new_crtc_state->has_psr2 != > > > psr- > > > > psr2_enabled; > > > + needs_to_disable |= new_crtc_state->has_sel_update > > > != > > > +psr->psr2_enabled; > > > needs_to_disable |= DISPLAY_VER(i915) < 11 && > > > new_crtc_state->wm_level_disabled; > > > > > > -- > > > 2.34.1 > >
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index ccaa4cb2809b..2c391714f28e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "sdp split: %s\n", str_enabled_disabled(pipe_config->sdp_split_enable)); - drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n", - str_enabled_disabled(pipe_config->has_psr), - str_enabled_disabled(pipe_config->has_psr2), - str_enabled_disabled(pipe_config->has_panel_replay), - str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); + drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", + str_enabled_disabled(pipe_config->has_psr), + str_enabled_disabled(pipe_config->has_sel_update), + str_enabled_disabled(pipe_config->has_panel_replay), + str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); } drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f45e5f02096d..c1aba4e8ac54 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, */ if (current_config->has_panel_replay || pipe_config->has_panel_replay) { PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(has_sel_update); PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); PIPE_CONF_CHECK_BOOL(has_panel_replay); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 62f7a30c37dc..6747c10da298 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1189,7 +1189,7 @@ struct intel_crtc_state { /* PSR is supported but might not be enabled due the lack of enabled planes */ bool has_psr; - bool has_psr2; + bool has_sel_update; bool enable_psr2_sel_fetch; bool enable_psr2_su_region_et; bool req_psr2_sdp_prior_scanline; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e05e25cd4a94..a7c406a9695f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, vsc); - } else if (crtc_state->has_psr2) { + } else if (crtc_state->has_psr && crtc_state->has_sel_update) { /* * [PSR2 without colorimetry] * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 151dcd0c45b6..984f13d8c0c8 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5b33335a9ae..a2f7d998d342 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - if (crtc_state->has_psr2) { + if (crtc_state->has_sel_update) { /* Enable ALPM at sink for psr2 */ if (!crtc_state->has_panel_replay) { drm_dp_dpcd_writeb(&intel_dp->aux, @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1672,7 +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr = true; } - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); if (!intel_dp->psr.psr2_enabled) @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; + needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled;