[RFC,v2,0/4] clk: thead: Add support for TH1520 AP_SUBSYS clock controller

Message

Drew Fustini April 27, 2024, 12:10 a.m. UTC

This series adds support for the AP sub-system clock controller in the
T-Head TH1520 [1]. Yangtao Li originally submitted this series in May
2023 [2]. Jisheng made additional improvements and then passed on the
work in progress to me.

Changes I made from the original series:
 - corrected the npu_clk enable bit
 - deduplicated CLK_NPU and CLK_NPU_AXI number in header
 - fixed c910_i0_clk reg typo
 - fixed checkpatch and dt_binding_check warnings 
 - rebased on v6.9-rc5
 - revised commit descriptions

Changes since my RFC v1 [4]:
 - squash the header file patch into the DT schema patch
 - describe the changes I made to original series in the cover letter
   instead of the individual patches
 - fix my typo in my email address

TODO:
I am again marking this as an RFC because there is feedback from v1 that
I have not yet addressed. I am posting what I currently have as other
patch series like the TH1520 I2C driver [4] could use the clk driver.

Emil commented that the input predivider is not handled correctly in
ccu_mdiv_recalc_rate(). The PLL multiplies the input frequency and
outputs "Foutvco". This is followed by a post divider to produce
"Foutpostdiv". However, some clocks derive directly from the "Foutvco"
Emil suggested this should really be modeled as two different clocks.

Emil aslo suggested that the rest of the clocks in this driver seem to
be generic gate and mux implementations that should probably be replaced
with devm_clk_hw_register_gate*() and devm_clk_hw_register_mux*().

I'll look to address the above issues in the next revision.

Thank you,
Drew

[1] https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
[2] https://lore.kernel.org/linux-riscv/[e-mail]/
[3] https://lore.kernel.org/lkml/[e-mail]/
[4] https://lore.kernel.org/linux-riscv/[e-mail]/

---
Drew Fustini (4):
      dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
      clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
      riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller
      riscv: dts: thead: Add clock to TH1520 mmc controllers

 .../bindings/clock/thead,th1520-clk-ap.yaml        |   65 ++
 MAINTAINERS                                        |    3 +
 arch/riscv/boot/dts/thead/th1520.dtsi              |   15 +-
 drivers/clk/Kconfig                                |    1 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/thead/Kconfig                          |   12 +
 drivers/clk/thead/Makefile                         |    2 +
 drivers/clk/thead/clk-th1520-ap.c                  | 1018 ++++++++++++++++++++
 include/dt-bindings/clock/thead,th1520-clk-ap.h    |   96 ++
 9 files changed, 1210 insertions(+), 3 deletions(-)
---
base-commit: 14396a29c3cfbd42b4ea5cd0a528264831524062
change-id: 20240426-th1520-clk-v2-134bfc9bddb1

Best regards,

Comments

Thomas Bonnefille May 2, 2024, 7:47 a.m. UTC | #1

On 4/27/24 2:10 AM, Drew Fustini wrote:
> This series adds support for the AP sub-system clock controller in the
> T-Head TH1520 [1]. Yangtao Li originally submitted this series in May
> 2023 [2]. Jisheng made additional improvements and then passed on the
> work in progress to me.
> 
> Changes I made from the original series:
>   - corrected the npu_clk enable bit
>   - deduplicated CLK_NPU and CLK_NPU_AXI number in header
>   - fixed c910_i0_clk reg typo
>   - fixed checkpatch and dt_binding_check warnings
>   - rebased on v6.9-rc5
>   - revised commit descriptions
> 
> Changes since my RFC v1 [4]:
>   - squash the header file patch into the DT schema patch
>   - describe the changes I made to original series in the cover letter
>     instead of the individual patches
>   - fix my typo in my email address
> 
> TODO:
> I am again marking this as an RFC because there is feedback from v1 that
> I have not yet addressed. I am posting what I currently have as other
> patch series like the TH1520 I2C driver [4] could use the clk driver.
> 
> Emil commented that the input predivider is not handled correctly in
> ccu_mdiv_recalc_rate(). The PLL multiplies the input frequency and
> outputs "Foutvco". This is followed by a post divider to produce
> "Foutpostdiv". However, some clocks derive directly from the "Foutvco"
> Emil suggested this should really be modeled as two different clocks.
> 
> Emil aslo suggested that the rest of the clocks in this driver seem to
> be generic gate and mux implementations that should probably be replaced
> with devm_clk_hw_register_gate*() and devm_clk_hw_register_mux*().
> 
> I'll look to address the above issues in the next revision.
> 
> Thank you,
> Drew
> 
> [1] https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
> [2] https://lore.kernel.org/linux-riscv/[e-mail]/
> [3] https://lore.kernel.org/lkml/[e-mail]/
> [4] https://lore.kernel.org/linux-riscv/[e-mail]/

Thank you ! It works on the Beagle-V Ahead :)

Tested-by: Thomas Bonnefille <[e-mail]>