| Message ID | 20240409120211.321153-1-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/mediatek: Add support for OF graphs | expand |
Hi Angelo, On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote: > This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa > NIO-12L with both hardcoded paths, OF graph support and partially > hardcoded paths (meaning main display through OF graph and external > display hardcoded, because of OVL_ADAPTOR). Is that make sense for you to add the DTS changes of these boards into this serie ? I asked because, IMHO, that could help to understand the serie.
Il 30/04/24 12:17, Alexandre Mergnat ha scritto: > Hi Angelo, > > On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote: >> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >> NIO-12L with both hardcoded paths, OF graph support and partially >> hardcoded paths (meaning main display through OF graph and external >> display hardcoded, because of OVL_ADAPTOR). > > Is that make sense for you to add the DTS changes of these boards into this serie ? > I asked because, IMHO, that could help to understand the serie. > Yes and no... but I imagine that you're asking this because you're trying to prepare something with a different SoC+board(s) combination :-) In that case, I'm preventively sorry because what follows here is not 100% perfectly tidy yet as I didn't mean to send the devicetree commits upstream before this series got picked.... ... but there you go - I'm sure that you won't mind and that the example will be more than good enough for you. Please note that one of the reasons why I didn't want to add this to the series is that the following changes show only a mere 50% of the reasons why we want OF graph support on mediatek-drm (but mainly, it's because I didn't have time to actually rebase etc :-P ) Cheers! Angelo .../boot/dts/mediatek/mt8195-cherry.dtsi | 65 +++++++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 153 +++++++++++++++++- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 24 +++ 3 files changed, 231 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 86d283ffe807..b05b6bbd457c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -267,12 +267,29 @@ &auxadc { status = "okay"; }; +&dither0_out { + remote-endpoint = <&dsc0_in>; +}; + &dp_intf0 { status = "okay"; - port { - dp_intf0_out: endpoint { - remote-endpoint = <&edp_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_intf0_in: endpoint { + remote-endpoint = <&merge0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; + }; }; }; }; @@ -287,6 +304,27 @@ dp_intf1_out: endpoint { }; }; +&dsc0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsc0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsc0_out: endpoint { + remote-endpoint = <&merge0_in>; + }; + }; + }; +}; + &edp_tx { status = "okay"; @@ -481,6 +519,27 @@ pmic@34 { }; }; +&merge0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge0_in: endpoint { + remote-endpoint = <&dsc0_out>; + }; + }; + + port@1 { + reg = <1>; + merge0_out: endpoint { + remote-endpoint = <&dp_intf0_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 88a0035a31a5..982572d7bfd8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3077,14 +3077,6 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells = <1>; }; - vdosys0: syscon@1c01a000 { - compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; - reg = <0 0x1c01a000 0 0x1000>; - mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; - #clock-cells = <1>; - }; - - jpgenc-master { compatible = "mediatek,mt8195-jpgenc"; power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; @@ -3143,6 +3135,38 @@ ovl0: ovl@1c000000 { clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&vdosys0_ep_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + #clock-cells = <1>; + + port { + vdosys0_ep_main: endpoint { + remote-endpoint = <&ovl0_in>; + }; + }; }; rdma0: rdma@1c002000 { @@ -3153,6 +3177,25 @@ rdma0: rdma@1c002000 { clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -3162,6 +3205,25 @@ color0: color@1c003000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -3171,6 +3233,25 @@ ccorr0: ccorr@1c004000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -3180,6 +3261,25 @@ aal0: aal@1c005000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -3189,6 +3289,25 @@ gamma0: gamma@1c006000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@1c007000 { @@ -3198,6 +3317,24 @@ dither0: dither@1c007000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + }; + }; + }; }; dsi0: dsi@1c008000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 7ab19b4e046f..b4a7dad2fea7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -1063,6 +1063,10 @@ &disp_pwm0 { status = "okay"; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + &dsi0 { status = "okay"; #address-cells = <1>; @@ -1089,6 +1093,25 @@ dsi_panel_in: endpoint { }; }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; +/* old hardcoded dsi stuff, disappear! ports { port { dsi_out: endpoint { @@ -1096,6 +1119,7 @@ dsi_out: endpoint { }; }; }; +*/ };
On 30/04/2024 13:33, AngeloGioacchino Del Regno wrote: > Il 30/04/24 12:17, Alexandre Mergnat ha scritto: >> Hi Angelo, >> >> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote: >>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >>> NIO-12L with both hardcoded paths, OF graph support and partially >>> hardcoded paths (meaning main display through OF graph and external >>> display hardcoded, because of OVL_ADAPTOR). >> >> Is that make sense for you to add the DTS changes of these boards into this serie ? >> I asked because, IMHO, that could help to understand the serie. >> > > Yes and no... but I imagine that you're asking this because you're trying to > prepare something with a different SoC+board(s) combination :-) > > In that case, I'm preventively sorry because what follows here is not 100% > perfectly tidy yet as I didn't mean to send the devicetree commits upstream > before this series got picked.... > > ... but there you go - I'm sure that you won't mind and that the example will > be more than good enough for you. > > Please note that one of the reasons why I didn't want to add this to the series > is that the following changes show only a mere 50% of the reasons why we want OF > graph support on mediatek-drm (but mainly, it's because I didn't have time to > actually rebase etc :-P ) Thanks for the explanations and examples. Unfortunately, I have 2 display but only one is working (the main: DSI0) when I use the dts method. I've probably missed something but I don't know what. In my "mmsys" node, if I swap display (the ext endpoint with the main endpoint), the DPI0 is working, but not the DSI0. I conclude my both paths are good. Then, I've put some trace into "mtk_drm_of_ddp_path_build" to check if it parse the two endpoint of the node. Both are parsed, but "of_ep.port" is always = 0. According to "of_graph_parse_endpoint" function, "port" is the value of the parent "reg", whereas "id" is the value of the endpoint "reg". So I replaced "of_ep.port" by "of_ep.id". Now I've of_ep.id = 0 for main and of_ep.id = 1 for EXT. Now I've the good CRTC path, I get this error: mediatek-drm mediatek-drm.1.auto: Invalid display hw pipeline. Last component: 54 (ret=-2) mediatek-drm mediatek-drm.1.auto: probe with driver mediatek-drm failed with error -22 After quick look, the "cpath" into "mtk_drm_of_ddp_path_build_one" (or deeper functions) seems not be used as it should, due to the previous "of_ep.port" => "of_ep.id" change of course. But I probably have to fix "of_ep.port" because I've mis-coded something. Just in case, I share you my diff: diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 1aa3426f561b..f660481d3fe8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -109,15 +109,51 @@ vsys_lcm_reg: regulator-vsys-lcm { }; }; +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + &dpi0 { pinctrl-0 = <&dpi_default_pins>; pinctrl-1 = <&dpi_idle_pins>; pinctrl-names = "default", "sleep"; status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; - port { - dpi_out: endpoint { - remote-endpoint = <&it66121_in>; + port@0 { + reg = <0>; + dpi0_in: endpoint { + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + reg = <1>; + dpi0_out: endpoint { + remote-endpoint = <&it66121_in>; + }; }; }; }; @@ -137,36 +173,28 @@ panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi_out>; + remote-endpoint = <&dsi0_out>; }; }; }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port { - dsi_out: endpoint { - remote-endpoint = <&panel_in>; + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; }; - }; -}; -&cpu0 { - proc-supply = <&mt6357_vproc_reg>; - sram-supply = <&mt6357_vsram_proc_reg>; -}; - -&cpu1 { - proc-supply = <&mt6357_vproc_reg>; - sram-supply = <&mt6357_vsram_proc_reg>; -}; - -&cpu2 { - proc-supply = <&mt6357_vproc_reg>; - sram-supply = <&mt6357_vsram_proc_reg>; -}; - -&cpu3 { - proc-supply = <&mt6357_vproc_reg>; - sram-supply = <&mt6357_vsram_proc_reg>; + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; }; ðernet { @@ -229,7 +257,7 @@ port@0 { reg = <0>; it66121_in: endpoint { bus-width = <12>; - remote-endpoint = <&dpi_out>; + remote-endpoint = <&dpi0_out>; }; }; @@ -557,6 +585,10 @@ &pwm { status = "okay"; }; +&rdma1_out { + remote-endpoint = <&dpi0_in>; +}; + &ssusb { dr_mode = "otg"; maximum-speed = "high-speed"; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index d34519a33c90..dbb559959a9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -762,6 +762,19 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8365-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; }; mutex: mutex@14001000 { @@ -801,6 +814,24 @@ ovl0: ovl@1400b000 { interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; iommus = <&iommu M4U_PORT_DISP_OVL0>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1400d000 { @@ -811,6 +842,24 @@ rdma0: rdma@1400d000 { iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,rdma-fifo-size = <5120>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1400f000 { @@ -819,6 +868,24 @@ color0: color@1400f000 { clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@14010000 { @@ -827,6 +894,24 @@ ccorr0: ccorr@14010000 { clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@14011000 { @@ -835,6 +920,24 @@ aal0: aal@14011000 { clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@14012000 { @@ -843,6 +946,24 @@ gamma0: gamma@14012000 { clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@14013000 { @@ -851,6 +972,23 @@ dither0: dither@14013000 { clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + }; + }; + }; }; dsi0: dsi@14014000 { @@ -874,6 +1012,23 @@ rdma1: rdma@14016000 { iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,rdma-fifo-size = <2048>; power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { + }; + }; + }; }; dpi0: dpi@14018000 { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index dacf4eaa3457..5992b7865310 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -230,22 +230,6 @@ static const unsigned int mt8195_mtk_ddp_ext[] = { DDP_COMPONENT_DP_INTF1, }; -static const unsigned int mt8365_mtk_ddp_main[] = { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSI0, -}; - -static const unsigned int mt8365_mtk_ddp_ext[] = { - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI0, -}; - static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -334,10 +318,6 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { - .main_path = mt8365_mtk_ddp_main, - .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main), - .ext_path = mt8365_mtk_ddp_ext, - .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext), .mmsys_dev_num = 1, };
Hi Angelo, On Tue Apr 30, 2024 at 1:33 PM CEST, AngeloGioacchino Del Regno wrote: > >> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa > >> NIO-12L with both hardcoded paths, OF graph support and partially > >> hardcoded paths (meaning main display through OF graph and external > >> display hardcoded, because of OVL_ADAPTOR). > > > > Is that make sense for you to add the DTS changes of these boards into this serie ? > > I asked because, IMHO, that could help to understand the serie. > > > > Yes and no... but I imagine that you're asking this because you're trying to > prepare something with a different SoC+board(s) combination :-) > > In that case, I'm preventively sorry because what follows here is not 100% > perfectly tidy yet as I didn't mean to send the devicetree commits upstream > before this series got picked.... > > ... but there you go - I'm sure that you won't mind and that the example will > be more than good enough for you. I've tested this series with the DSI0 output and it works. Nice! No need for my DSI0 patch for the MT8395 anymore. But I can't get it to work with the DisplayPort output, that is the dp_intf1/dp_tx interface. I don' know how the pipeline have to look like. The functional spec seems to be ambiguous on this. The text seem to refer to the second vdosys but there is also a diagram where you can use the first vdosys and dsc0. If you have any pointers for me, I'm all ears :) -michael
Il 06/05/24 12:02, Michael Walle ha scritto: > Hi Angelo, > > On Tue Apr 30, 2024 at 1:33 PM CEST, AngeloGioacchino Del Regno wrote: >>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >>>> NIO-12L with both hardcoded paths, OF graph support and partially >>>> hardcoded paths (meaning main display through OF graph and external >>>> display hardcoded, because of OVL_ADAPTOR). >>> >>> Is that make sense for you to add the DTS changes of these boards into this serie ? >>> I asked because, IMHO, that could help to understand the serie. >>> >> >> Yes and no... but I imagine that you're asking this because you're trying to >> prepare something with a different SoC+board(s) combination :-) >> >> In that case, I'm preventively sorry because what follows here is not 100% >> perfectly tidy yet as I didn't mean to send the devicetree commits upstream >> before this series got picked.... >> >> ... but there you go - I'm sure that you won't mind and that the example will >> be more than good enough for you. > > I've tested this series with the DSI0 output and it works. Nice! No > need for my DSI0 patch for the MT8395 anymore. > > But I can't get it to work with the DisplayPort output, that is the > dp_intf1/dp_tx interface. I don' know how the pipeline have to look > like. The functional spec seems to be ambiguous on this. The text > seem to refer to the second vdosys but there is also a diagram where > you can use the first vdosys and dsc0. If you have any pointers for > me, I'm all ears :) > The problem with this is that you need DDP_COMPONENT_DRM_OVL_ADAPTOR... which is a software thing and not HW, so that can't be described in devicetree. The only thing this series won't deal with is exactly that. It's relatively easy, though, to add support for the OVL_ADAPTOR... as it would be just a matter of checking if any of the components in the pipeline contain a compatible that is in the OVL_ADAPTOR compatible list. I'll try to add that up today, let's see what I can do. Cheers, Angelo
Il 06/05/24 12:56, AngeloGioacchino Del Regno ha scritto: > Il 06/05/24 12:02, Michael Walle ha scritto: >> Hi Angelo, >> >> On Tue Apr 30, 2024 at 1:33 PM CEST, AngeloGioacchino Del Regno wrote: >>>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >>>>> NIO-12L with both hardcoded paths, OF graph support and partially >>>>> hardcoded paths (meaning main display through OF graph and external >>>>> display hardcoded, because of OVL_ADAPTOR). >>>> >>>> Is that make sense for you to add the DTS changes of these boards into this >>>> serie ? >>>> I asked because, IMHO, that could help to understand the serie. >>>> >>> >>> Yes and no... but I imagine that you're asking this because you're trying to >>> prepare something with a different SoC+board(s) combination :-) >>> >>> In that case, I'm preventively sorry because what follows here is not 100% >>> perfectly tidy yet as I didn't mean to send the devicetree commits upstream >>> before this series got picked.... >>> >>> ... but there you go - I'm sure that you won't mind and that the example will >>> be more than good enough for you. >> >> I've tested this series with the DSI0 output and it works. Nice! No >> need for my DSI0 patch for the MT8395 anymore. >> >> But I can't get it to work with the DisplayPort output, that is the >> dp_intf1/dp_tx interface. I don' know how the pipeline have to look >> like. The functional spec seems to be ambiguous on this. The text >> seem to refer to the second vdosys but there is also a diagram where >> you can use the first vdosys and dsc0. If you have any pointers for >> me, I'm all ears :) >> > > > The problem with this is that you need DDP_COMPONENT_DRM_OVL_ADAPTOR... which is > a software thing and not HW, so that can't be described in devicetree. > > The only thing this series won't deal with is exactly that. Sorry, no, I got confused. The series *does* already deal with that, as the pipeline is built before the check for OVL_ADAPTOR components, so that will get probed. What I got confused about is the fact that I promised myself to cleanup the support for that OVL_ADAPTOR thing (which is unrelated to this series, even...), but again, this series will still get that probed anyway. Anyway. The pipeline for DP1 should be simply VDOSYS 1 -> MERGE 5 -> DP_INTF 1 -> DP (eDP on VDOSYS 0 -> MERGE 0 --- DP on VDOSYS 1 -> MERGE 5) Cheers, Angelo > > It's relatively easy, though, to add support for the OVL_ADAPTOR... as it would > be just a matter of checking if any of the components in the pipeline contain a > compatible that is in the OVL_ADAPTOR compatible list. > > I'll try to add that up today, let's see what I can do. >
Hi Angelo, On Mon May 6, 2024 at 1:22 PM CEST, AngeloGioacchino Del Regno wrote: > > The problem with this is that you need DDP_COMPONENT_DRM_OVL_ADAPTOR... which is > > a software thing and not HW, so that can't be described in devicetree. > > > > The only thing this series won't deal with is exactly that. > > Sorry, no, I got confused. > > The series *does* already deal with that, as the pipeline is built before the check > for OVL_ADAPTOR components, so that will get probed. Are you sure? Because who is actually adding the OVL_ADAPTOR to the path? It looks like your patch will walk the graph and add all the components according to their compatible string. And since the OVL_ADAPTOR is virtual and doesn't have a node.. -michael
Il 06/05/24 15:17, Michael Walle ha scritto: > Hi Angelo, > > On Mon May 6, 2024 at 1:22 PM CEST, AngeloGioacchino Del Regno wrote: >>> The problem with this is that you need DDP_COMPONENT_DRM_OVL_ADAPTOR... which is >>> a software thing and not HW, so that can't be described in devicetree. >>> >>> The only thing this series won't deal with is exactly that. >> >> Sorry, no, I got confused. >> >> The series *does* already deal with that, as the pipeline is built before the check >> for OVL_ADAPTOR components, so that will get probed. > > Are you sure? Because who is actually adding the OVL_ADAPTOR to the > path? It looks like your patch will walk the graph and add all the > components according to their compatible string. And since the > OVL_ADAPTOR is virtual and doesn't have a node.. > I shouldn't look at code while having a flu. if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { ...but yes nothing adds the mmsys_comp for OVL_ADAPTOR. Needs to be addressed, will do that asap.
Hi Angelo, Gentle ping because I'm stuck if I rebase my serie on top of yours. On 02/05/2024 18:53, Alexandre Mergnat wrote: > > > On 30/04/2024 13:33, AngeloGioacchino Del Regno wrote: >> Il 30/04/24 12:17, Alexandre Mergnat ha scritto: >>> Hi Angelo, >>> >>> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote: >>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >>>> NIO-12L with both hardcoded paths, OF graph support and partially >>>> hardcoded paths (meaning main display through OF graph and external >>>> display hardcoded, because of OVL_ADAPTOR). >>> >>> Is that make sense for you to add the DTS changes of these boards into this serie ? >>> I asked because, IMHO, that could help to understand the serie. >>> >> >> Yes and no... but I imagine that you're asking this because you're trying to >> prepare something with a different SoC+board(s) combination :-) >> >> In that case, I'm preventively sorry because what follows here is not 100% >> perfectly tidy yet as I didn't mean to send the devicetree commits upstream >> before this series got picked.... >> >> ... but there you go - I'm sure that you won't mind and that the example will >> be more than good enough for you. >> >> Please note that one of the reasons why I didn't want to add this to the series >> is that the following changes show only a mere 50% of the reasons why we want OF >> graph support on mediatek-drm (but mainly, it's because I didn't have time to >> actually rebase etc :-P ) > > Thanks for the explanations and examples. > Unfortunately, I have 2 display but only one is working (the main: DSI0) when I use the dts method. > I've probably missed something but I don't know what. > > In my "mmsys" node, if I swap display (the ext endpoint with the main endpoint), the DPI0 is > working, but not the DSI0. I conclude my both paths are good. > > Then, I've put some trace into "mtk_drm_of_ddp_path_build" to check if it parse the two endpoint of > the node. Both are parsed, but "of_ep.port" is always = 0. According to "of_graph_parse_endpoint" > function, "port" is the value of the parent "reg", whereas "id" is the value of the endpoint "reg". > So I replaced "of_ep.port" by "of_ep.id". Now I've of_ep.id = 0 for main and of_ep.id = 1 for EXT. > > Now I've the good CRTC path, I get this error: > mediatek-drm mediatek-drm.1.auto: Invalid display hw pipeline. Last component: 54 (ret=-2) > mediatek-drm mediatek-drm.1.auto: probe with driver mediatek-drm failed with error -22 > > After quick look, the "cpath" into "mtk_drm_of_ddp_path_build_one" (or deeper functions) seems not > be used as it should, due to the previous "of_ep.port" => "of_ep.id" change of course. > > But I probably have to fix "of_ep.port" because I've mis-coded something. Just in case, I share you > my diff: > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > index 1aa3426f561b..f660481d3fe8 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > @@ -109,15 +109,51 @@ vsys_lcm_reg: regulator-vsys-lcm { > }; > }; > > +&cpu0 { > + proc-supply = <&mt6357_vproc_reg>; > + sram-supply = <&mt6357_vsram_proc_reg>; > +}; > + > +&cpu1 { > + proc-supply = <&mt6357_vproc_reg>; > + sram-supply = <&mt6357_vsram_proc_reg>; > +}; > + > +&cpu2 { > + proc-supply = <&mt6357_vproc_reg>; > + sram-supply = <&mt6357_vsram_proc_reg>; > +}; > + > +&cpu3 { > + proc-supply = <&mt6357_vproc_reg>; > + sram-supply = <&mt6357_vsram_proc_reg>; > +}; > + > +&dither0_out { > + remote-endpoint = <&dsi0_in>; > +}; > + > &dpi0 { > pinctrl-0 = <&dpi_default_pins>; > pinctrl-1 = <&dpi_idle_pins>; > pinctrl-names = "default", "sleep"; > status = "okay"; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > > - port { > - dpi_out: endpoint { > - remote-endpoint = <&it66121_in>; > + port@0 { > + reg = <0>; > + dpi0_in: endpoint { > + remote-endpoint = <&rdma1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpi0_out: endpoint { > + remote-endpoint = <&it66121_in>; > + }; > }; > }; > }; > @@ -137,36 +173,28 @@ panel@0 { > > port { > panel_in: endpoint { > - remote-endpoint = <&dsi_out>; > + remote-endpoint = <&dsi0_out>; > }; > }; > }; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > > - port { > - dsi_out: endpoint { > - remote-endpoint = <&panel_in>; > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dither0_out>; > + }; > }; > - }; > -}; > > -&cpu0 { > - proc-supply = <&mt6357_vproc_reg>; > - sram-supply = <&mt6357_vsram_proc_reg>; > -}; > - > -&cpu1 { > - proc-supply = <&mt6357_vproc_reg>; > - sram-supply = <&mt6357_vsram_proc_reg>; > -}; > - > -&cpu2 { > - proc-supply = <&mt6357_vproc_reg>; > - sram-supply = <&mt6357_vsram_proc_reg>; > -}; > - > -&cpu3 { > - proc-supply = <&mt6357_vproc_reg>; > - sram-supply = <&mt6357_vsram_proc_reg>; > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > }; > > ðernet { > @@ -229,7 +257,7 @@ port@0 { > reg = <0>; > it66121_in: endpoint { > bus-width = <12>; > - remote-endpoint = <&dpi_out>; > + remote-endpoint = <&dpi0_out>; > }; > }; > > @@ -557,6 +585,10 @@ &pwm { > status = "okay"; > }; > > +&rdma1_out { > + remote-endpoint = <&dpi0_in>; > +}; > + > &ssusb { > dr_mode = "otg"; > maximum-speed = "high-speed"; > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index d34519a33c90..dbb559959a9d 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -762,6 +762,19 @@ mmsys: syscon@14000000 { > compatible = "mediatek,mt8365-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > #clock-cells = <1>; > + port { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mmsys_main: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&ovl0_in>; > + }; > + mmsys_ext: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&rdma1_in>; > + }; > + }; > }; > > mutex: mutex@14001000 { > @@ -801,6 +814,24 @@ ovl0: ovl@1400b000 { > interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; > iommus = <&iommu M4U_PORT_DISP_OVL0>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + ovl0_in: endpoint { > + remote-endpoint = <&mmsys_main>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + ovl0_out: endpoint { > + remote-endpoint = <&rdma0_in>; > + }; > + }; > + }; > }; > > rdma0: rdma@1400d000 { > @@ -811,6 +842,24 @@ rdma0: rdma@1400d000 { > iommus = <&iommu M4U_PORT_DISP_RDMA0>; > mediatek,rdma-fifo-size = <5120>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + rdma0_in: endpoint { > + remote-endpoint = <&ovl0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + rdma0_out: endpoint { > + remote-endpoint = <&color0_in>; > + }; > + }; > + }; > }; > > color0: color@1400f000 { > @@ -819,6 +868,24 @@ color0: color@1400f000 { > clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; > interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + color0_in: endpoint { > + remote-endpoint = <&rdma0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + color0_out: endpoint { > + remote-endpoint = <&ccorr0_in>; > + }; > + }; > + }; > }; > > ccorr0: ccorr@14010000 { > @@ -827,6 +894,24 @@ ccorr0: ccorr@14010000 { > clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; > interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + ccorr0_in: endpoint { > + remote-endpoint = <&color0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + ccorr0_out: endpoint { > + remote-endpoint = <&aal0_in>; > + }; > + }; > + }; > }; > > aal0: aal@14011000 { > @@ -835,6 +920,24 @@ aal0: aal@14011000 { > clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; > interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + aal0_in: endpoint { > + remote-endpoint = <&ccorr0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + aal0_out: endpoint { > + remote-endpoint = <&gamma0_in>; > + }; > + }; > + }; > }; > > gamma0: gamma@14012000 { > @@ -843,6 +946,24 @@ gamma0: gamma@14012000 { > clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; > interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + gamma0_in: endpoint { > + remote-endpoint = <&aal0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + gamma0_out: endpoint { > + remote-endpoint = <&dither0_in>; > + }; > + }; > + }; > }; > > dither0: dither@14013000 { > @@ -851,6 +972,23 @@ dither0: dither@14013000 { > clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; > interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dither0_in: endpoint { > + remote-endpoint = <&gamma0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dither0_out: endpoint { > + }; > + }; > + }; > }; > > dsi0: dsi@14014000 { > @@ -874,6 +1012,23 @@ rdma1: rdma@14016000 { > iommus = <&iommu M4U_PORT_DISP_RDMA1>; > mediatek,rdma-fifo-size = <2048>; > power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + rdma1_in: endpoint { > + remote-endpoint = <&mmsys_ext>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + rdma1_out: endpoint { > + }; > + }; > + }; > }; > > dpi0: dpi@14018000 { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index dacf4eaa3457..5992b7865310 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -230,22 +230,6 @@ static const unsigned int mt8195_mtk_ddp_ext[] = { > DDP_COMPONENT_DP_INTF1, > }; > > -static const unsigned int mt8365_mtk_ddp_main[] = { > - DDP_COMPONENT_OVL0, > - DDP_COMPONENT_RDMA0, > - DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_CCORR, > - DDP_COMPONENT_AAL0, > - DDP_COMPONENT_GAMMA, > - DDP_COMPONENT_DITHER0, > - DDP_COMPONENT_DSI0, > -}; > - > -static const unsigned int mt8365_mtk_ddp_ext[] = { > - DDP_COMPONENT_RDMA1, > - DDP_COMPONENT_DPI0, > -}; > - > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -334,10 +318,6 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { > }; > > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { > - .main_path = mt8365_mtk_ddp_main, > - .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main), > - .ext_path = mt8365_mtk_ddp_ext, > - .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext), > .mmsys_dev_num = 1, > }; > > > > -- > Regards, > Alexandre
Il 14/05/24 11:46, Alexandre Mergnat ha scritto: > Hi Angelo, > > Gentle ping because I'm stuck if I rebase my serie on top of yours. > Sorry, I was unable to find time to get back to this... I plan to look at it between today and tomorrow. In the meanwhile - does your platform use OVL_ADAPTOR? If it does, that's the actual issue; otherwise, there may be some mistake on your side, because the EPs' ports<->ids relationship was verified before sending this to the lists. Cheers, Angelo > On 02/05/2024 18:53, Alexandre Mergnat wrote: >> >> >> On 30/04/2024 13:33, AngeloGioacchino Del Regno wrote: >>> Il 30/04/24 12:17, Alexandre Mergnat ha scritto: >>>> Hi Angelo, >>>> >>>> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote: >>>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa >>>>> NIO-12L with both hardcoded paths, OF graph support and partially >>>>> hardcoded paths (meaning main display through OF graph and external >>>>> display hardcoded, because of OVL_ADAPTOR). >>>> >>>> Is that make sense for you to add the DTS changes of these boards into this >>>> serie ? >>>> I asked because, IMHO, that could help to understand the serie. >>>> >>> >>> Yes and no... but I imagine that you're asking this because you're trying to >>> prepare something with a different SoC+board(s) combination :-) >>> >>> In that case, I'm preventively sorry because what follows here is not 100% >>> perfectly tidy yet as I didn't mean to send the devicetree commits upstream >>> before this series got picked.... >>> >>> ... but there you go - I'm sure that you won't mind and that the example will >>> be more than good enough for you. >>> >>> Please note that one of the reasons why I didn't want to add this to the series >>> is that the following changes show only a mere 50% of the reasons why we want OF >>> graph support on mediatek-drm (but mainly, it's because I didn't have time to >>> actually rebase etc :-P ) >> >> Thanks for the explanations and examples. >> Unfortunately, I have 2 display but only one is working (the main: DSI0) when I >> use the dts method. >> I've probably missed something but I don't know what. >> >> In my "mmsys" node, if I swap display (the ext endpoint with the main endpoint), >> the DPI0 is working, but not the DSI0. I conclude my both paths are good. >> >> Then, I've put some trace into "mtk_drm_of_ddp_path_build" to check if it parse >> the two endpoint of the node. Both are parsed, but "of_ep.port" is always = 0. >> According to "of_graph_parse_endpoint" function, "port" is the value of the >> parent "reg", whereas "id" is the value of the endpoint "reg". >> So I replaced "of_ep.port" by "of_ep.id". Now I've of_ep.id = 0 for main and >> of_ep.id = 1 for EXT. >> >> Now I've the good CRTC path, I get this error: >> mediatek-drm mediatek-drm.1.auto: Invalid display hw pipeline. Last component: >> 54 (ret=-2) >> mediatek-drm mediatek-drm.1.auto: probe with driver mediatek-drm failed with >> error -22 >> >> After quick look, the "cpath" into "mtk_drm_of_ddp_path_build_one" (or deeper >> functions) seems not be used as it should, due to the previous "of_ep.port" => >> "of_ep.id" change of course. >> >> But I probably have to fix "of_ep.port" because I've mis-coded something. Just in >> case, I share you my diff: >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts >> b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts >> index 1aa3426f561b..f660481d3fe8 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts >> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts >> @@ -109,15 +109,51 @@ vsys_lcm_reg: regulator-vsys-lcm { >> }; >> }; >> >> +&cpu0 { >> + proc-supply = <&mt6357_vproc_reg>; >> + sram-supply = <&mt6357_vsram_proc_reg>; >> +}; >> + >> +&cpu1 { >> + proc-supply = <&mt6357_vproc_reg>; >> + sram-supply = <&mt6357_vsram_proc_reg>; >> +}; >> + >> +&cpu2 { >> + proc-supply = <&mt6357_vproc_reg>; >> + sram-supply = <&mt6357_vsram_proc_reg>; >> +}; >> + >> +&cpu3 { >> + proc-supply = <&mt6357_vproc_reg>; >> + sram-supply = <&mt6357_vsram_proc_reg>; >> +}; >> + >> +&dither0_out { >> + remote-endpoint = <&dsi0_in>; >> +}; >> + >> &dpi0 { >> pinctrl-0 = <&dpi_default_pins>; >> pinctrl-1 = <&dpi_idle_pins>; >> pinctrl-names = "default", "sleep"; >> status = "okay"; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - port { >> - dpi_out: endpoint { >> - remote-endpoint = <&it66121_in>; >> + port@0 { >> + reg = <0>; >> + dpi0_in: endpoint { >> + remote-endpoint = <&rdma1_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpi0_out: endpoint { >> + remote-endpoint = <&it66121_in>; >> + }; >> }; >> }; >> }; >> @@ -137,36 +173,28 @@ panel@0 { >> >> port { >> panel_in: endpoint { >> - remote-endpoint = <&dsi_out>; >> + remote-endpoint = <&dsi0_out>; >> }; >> }; >> }; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - port { >> - dsi_out: endpoint { >> - remote-endpoint = <&panel_in>; >> + port@0 { >> + reg = <0>; >> + dsi0_in: endpoint { >> + remote-endpoint = <&dither0_out>; >> + }; >> }; >> - }; >> -}; >> >> -&cpu0 { >> - proc-supply = <&mt6357_vproc_reg>; >> - sram-supply = <&mt6357_vsram_proc_reg>; >> -}; >> - >> -&cpu1 { >> - proc-supply = <&mt6357_vproc_reg>; >> - sram-supply = <&mt6357_vsram_proc_reg>; >> -}; >> - >> -&cpu2 { >> - proc-supply = <&mt6357_vproc_reg>; >> - sram-supply = <&mt6357_vsram_proc_reg>; >> -}; >> - >> -&cpu3 { >> - proc-supply = <&mt6357_vproc_reg>; >> - sram-supply = <&mt6357_vsram_proc_reg>; >> + port@1 { >> + reg = <1>; >> + dsi0_out: endpoint { >> + remote-endpoint = <&panel_in>; >> + }; >> + }; >> + }; >> }; >> >> ðernet { >> @@ -229,7 +257,7 @@ port@0 { >> reg = <0>; >> it66121_in: endpoint { >> bus-width = <12>; >> - remote-endpoint = <&dpi_out>; >> + remote-endpoint = <&dpi0_out>; >> }; >> }; >> >> @@ -557,6 +585,10 @@ &pwm { >> status = "okay"; >> }; >> >> +&rdma1_out { >> + remote-endpoint = <&dpi0_in>; >> +}; >> + >> &ssusb { >> dr_mode = "otg"; >> maximum-speed = "high-speed"; >> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi >> b/arch/arm64/boot/dts/mediatek/mt8365.dtsi >> index d34519a33c90..dbb559959a9d 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi >> @@ -762,6 +762,19 @@ mmsys: syscon@14000000 { >> compatible = "mediatek,mt8365-mmsys", "syscon"; >> reg = <0 0x14000000 0 0x1000>; >> #clock-cells = <1>; >> + port { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + mmsys_main: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&ovl0_in>; >> + }; >> + mmsys_ext: endpoint@1 { >> + reg = <1>; >> + remote-endpoint = <&rdma1_in>; >> + }; >> + }; >> }; >> >> mutex: mutex@14001000 { >> @@ -801,6 +814,24 @@ ovl0: ovl@1400b000 { >> interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; >> iommus = <&iommu M4U_PORT_DISP_OVL0>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + ovl0_in: endpoint { >> + remote-endpoint = <&mmsys_main>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + ovl0_out: endpoint { >> + remote-endpoint = <&rdma0_in>; >> + }; >> + }; >> + }; >> }; >> >> rdma0: rdma@1400d000 { >> @@ -811,6 +842,24 @@ rdma0: rdma@1400d000 { >> iommus = <&iommu M4U_PORT_DISP_RDMA0>; >> mediatek,rdma-fifo-size = <5120>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + rdma0_in: endpoint { >> + remote-endpoint = <&ovl0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + rdma0_out: endpoint { >> + remote-endpoint = <&color0_in>; >> + }; >> + }; >> + }; >> }; >> >> color0: color@1400f000 { >> @@ -819,6 +868,24 @@ color0: color@1400f000 { >> clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; >> interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + color0_in: endpoint { >> + remote-endpoint = <&rdma0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + color0_out: endpoint { >> + remote-endpoint = <&ccorr0_in>; >> + }; >> + }; >> + }; >> }; >> >> ccorr0: ccorr@14010000 { >> @@ -827,6 +894,24 @@ ccorr0: ccorr@14010000 { >> clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; >> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + ccorr0_in: endpoint { >> + remote-endpoint = <&color0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + ccorr0_out: endpoint { >> + remote-endpoint = <&aal0_in>; >> + }; >> + }; >> + }; >> }; >> >> aal0: aal@14011000 { >> @@ -835,6 +920,24 @@ aal0: aal@14011000 { >> clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; >> interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + aal0_in: endpoint { >> + remote-endpoint = <&ccorr0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + aal0_out: endpoint { >> + remote-endpoint = <&gamma0_in>; >> + }; >> + }; >> + }; >> }; >> >> gamma0: gamma@14012000 { >> @@ -843,6 +946,24 @@ gamma0: gamma@14012000 { >> clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; >> interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + gamma0_in: endpoint { >> + remote-endpoint = <&aal0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + gamma0_out: endpoint { >> + remote-endpoint = <&dither0_in>; >> + }; >> + }; >> + }; >> }; >> >> dither0: dither@14013000 { >> @@ -851,6 +972,23 @@ dither0: dither@14013000 { >> clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; >> interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + dither0_in: endpoint { >> + remote-endpoint = <&gamma0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dither0_out: endpoint { >> + }; >> + }; >> + }; >> }; >> >> dsi0: dsi@14014000 { >> @@ -874,6 +1012,23 @@ rdma1: rdma@14016000 { >> iommus = <&iommu M4U_PORT_DISP_RDMA1>; >> mediatek,rdma-fifo-size = <2048>; >> power-domains = <&spm MT8365_POWER_DOMAIN_MM>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + rdma1_in: endpoint { >> + remote-endpoint = <&mmsys_ext>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + rdma1_out: endpoint { >> + }; >> + }; >> + }; >> }; >> >> dpi0: dpi@14018000 { >> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c >> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c >> index dacf4eaa3457..5992b7865310 100644 >> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c >> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c >> @@ -230,22 +230,6 @@ static const unsigned int mt8195_mtk_ddp_ext[] = { >> DDP_COMPONENT_DP_INTF1, >> }; >> >> -static const unsigned int mt8365_mtk_ddp_main[] = { >> - DDP_COMPONENT_OVL0, >> - DDP_COMPONENT_RDMA0, >> - DDP_COMPONENT_COLOR0, >> - DDP_COMPONENT_CCORR, >> - DDP_COMPONENT_AAL0, >> - DDP_COMPONENT_GAMMA, >> - DDP_COMPONENT_DITHER0, >> - DDP_COMPONENT_DSI0, >> -}; >> - >> -static const unsigned int mt8365_mtk_ddp_ext[] = { >> - DDP_COMPONENT_RDMA1, >> - DDP_COMPONENT_DPI0, >> -}; >> - >> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { >> .main_path = mt2701_mtk_ddp_main, >> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), >> @@ -334,10 +318,6 @@ static const struct mtk_mmsys_driver_data >> mt8195_vdosys1_driver_data = { >> }; >> >> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { >> - .main_path = mt8365_mtk_ddp_main, >> - .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main), >> - .ext_path = mt8365_mtk_ddp_ext, >> - .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext), >> .mmsys_dev_num = 1, >> }; >> >> >> >> -- >> Regards, >> Alexandre >