diff mbox series

[v2,18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()

Message ID a35ae0f50258d4c4b8b6381bec9933f17105091a.1714606359.git.balaton@eik.bme.hu (mailing list archive)
State New, archived
Headers show
Series Misc PPC exception and BookE MMU clean ups | expand

Commit Message

BALATON Zoltan May 1, 2024, 11:43 p.m. UTC 
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 target/ppc/mmu_common.c | 319 ++++++++++++++++++++--------------------
 1 file changed, 159 insertions(+), 160 deletions(-)

Comments

Nicholas Piggin May 7, 2024, 10:06 a.m. UTC | #1 
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Instead of putting a large block of code in an if, invert the
> condition and return early to be able to deindent the code block.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>  target/ppc/mmu_common.c | 319 ++++++++++++++++++++--------------------
>  1 file changed, 159 insertions(+), 160 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 28847c32f2..2487b4deff 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1265,187 +1265,186 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
>          *protp = ctx.prot;
>          *psizep = TARGET_PAGE_BITS;
>          return true;
> +    } else if (!guest_visible) {
> +        return false;
>      }

Acked-by: Nicholas Piggin <npiggin@gmail.com>

>  
> -    if (guest_visible) {
> -        log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> -        if (type == ACCESS_CODE) {
> -            switch (ret) {
> -            case -1:
> -                /* No matches in page tables or TLB */
> -                switch (env->mmu_model) {
> -                case POWERPC_MMU_SOFT_6xx:
> -                    cs->exception_index = POWERPC_EXCP_IFTLB;
> -                    env->error_code = 1 << 18;
> -                    env->spr[SPR_IMISS] = eaddr;
> -                    env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
> -                    goto tlb_miss;
> -                case POWERPC_MMU_SOFT_4xx:
> -                    cs->exception_index = POWERPC_EXCP_ITLB;
> -                    env->error_code = 0;
> -                    env->spr[SPR_40x_DEAR] = eaddr;
> -                    env->spr[SPR_40x_ESR] = 0x00000000;
> -                    break;
> -                case POWERPC_MMU_BOOKE206:
> -                    booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
> -                    /* fall through */
> -                case POWERPC_MMU_BOOKE:
> -                    cs->exception_index = POWERPC_EXCP_ITLB;
> -                    env->error_code = 0;
> -                    env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
> -                    break;
> -                case POWERPC_MMU_REAL:
> -                    cpu_abort(cs, "PowerPC in real mode should never raise "
> -                              "any MMU exceptions\n");
> -                default:
> -                    cpu_abort(cs, "Unknown or invalid MMU model\n");
> -                }
> +    log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> +    if (type == ACCESS_CODE) {
> +        switch (ret) {
> +        case -1:
> +            /* No matches in page tables or TLB */
> +            switch (env->mmu_model) {
> +            case POWERPC_MMU_SOFT_6xx:
> +                cs->exception_index = POWERPC_EXCP_IFTLB;
> +                env->error_code = 1 << 18;
> +                env->spr[SPR_IMISS] = eaddr;
> +                env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
> +                goto tlb_miss;
> +            case POWERPC_MMU_SOFT_4xx:
> +                cs->exception_index = POWERPC_EXCP_ITLB;
> +                env->error_code = 0;
> +                env->spr[SPR_40x_DEAR] = eaddr;
> +                env->spr[SPR_40x_ESR] = 0x00000000;
>                  break;
> -            case -2:
> -                /* Access rights violation */
> -                cs->exception_index = POWERPC_EXCP_ISI;
> -                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                    env->error_code = 0;
> -                } else {
> -                    env->error_code = 0x08000000;
> -                }
> +            case POWERPC_MMU_BOOKE206:
> +                booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
> +                /* fall through */
> +            case POWERPC_MMU_BOOKE:
> +                cs->exception_index = POWERPC_EXCP_ITLB;
> +                env->error_code = 0;
> +                env->spr[SPR_BOOKE_DEAR] = eaddr;
> +                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
>                  break;
> -            case -3:
> -                /* No execute protection violation */
> -                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                    env->spr[SPR_BOOKE_ESR] = 0x00000000;
> -                    env->error_code = 0;
> +            case POWERPC_MMU_REAL:
> +                cpu_abort(cs, "PowerPC in real mode should never raise "
> +                              "any MMU exceptions\n");
> +            default:
> +                cpu_abort(cs, "Unknown or invalid MMU model\n");
> +            }
> +            break;
> +        case -2:
> +            /* Access rights violation */
> +            cs->exception_index = POWERPC_EXCP_ISI;
> +            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> +                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> +                env->error_code = 0;
> +            } else {
> +                env->error_code = 0x08000000;
> +            }
> +            break;
> +        case -3:
> +            /* No execute protection violation */
> +            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> +                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> +                env->spr[SPR_BOOKE_ESR] = 0x00000000;
> +                env->error_code = 0;
> +            } else {
> +                env->error_code = 0x10000000;
> +            }
> +            cs->exception_index = POWERPC_EXCP_ISI;
> +            break;
> +        case -4:
> +            /* Direct store exception */
> +            /* No code fetch is allowed in direct-store areas */
> +            cs->exception_index = POWERPC_EXCP_ISI;
> +            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> +                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> +                env->error_code = 0;
> +            } else {
> +                env->error_code = 0x10000000;
> +            }
> +            break;
> +        }
> +    } else {
> +        switch (ret) {
> +        case -1:
> +            /* No matches in page tables or TLB */
> +            switch (env->mmu_model) {
> +            case POWERPC_MMU_SOFT_6xx:
> +                if (access_type == MMU_DATA_STORE) {
> +                    cs->exception_index = POWERPC_EXCP_DSTLB;
> +                    env->error_code = 1 << 16;
>                  } else {
> -                    env->error_code = 0x10000000;
> +                    cs->exception_index = POWERPC_EXCP_DLTLB;
> +                    env->error_code = 0;
>                  }
> -                cs->exception_index = POWERPC_EXCP_ISI;
> +                env->spr[SPR_DMISS] = eaddr;
> +                env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
> +            tlb_miss:
> +                env->error_code |= ctx.key << 19;
> +                env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
> +                  get_pteg_offset32(cpu, ctx.hash[0]);
> +                env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
> +                  get_pteg_offset32(cpu, ctx.hash[1]);
>                  break;
> -            case -4:
> -                /* Direct store exception */
> -                /* No code fetch is allowed in direct-store areas */
> -                cs->exception_index = POWERPC_EXCP_ISI;
> -                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                    env->error_code = 0;
> +            case POWERPC_MMU_SOFT_4xx:
> +                cs->exception_index = POWERPC_EXCP_DTLB;
> +                env->error_code = 0;
> +                env->spr[SPR_40x_DEAR] = eaddr;
> +                if (access_type == MMU_DATA_STORE) {
> +                    env->spr[SPR_40x_ESR] = 0x00800000;
>                  } else {
> -                    env->error_code = 0x10000000;
> +                    env->spr[SPR_40x_ESR] = 0x00000000;
>                  }
>                  break;
> -            }
> -        } else {
> -            switch (ret) {
> -            case -1:
> -                /* No matches in page tables or TLB */
> -                switch (env->mmu_model) {
> -                case POWERPC_MMU_SOFT_6xx:
> -                    if (access_type == MMU_DATA_STORE) {
> -                        cs->exception_index = POWERPC_EXCP_DSTLB;
> -                        env->error_code = 1 << 16;
> -                    } else {
> -                        cs->exception_index = POWERPC_EXCP_DLTLB;
> -                        env->error_code = 0;
> -                    }
> -                    env->spr[SPR_DMISS] = eaddr;
> -                    env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
> -                tlb_miss:
> -                    env->error_code |= ctx.key << 19;
> -                    env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
> -                        get_pteg_offset32(cpu, ctx.hash[0]);
> -                    env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
> -                        get_pteg_offset32(cpu, ctx.hash[1]);
> -                    break;
> -                case POWERPC_MMU_SOFT_4xx:
> -                    cs->exception_index = POWERPC_EXCP_DTLB;
> -                    env->error_code = 0;
> -                    env->spr[SPR_40x_DEAR] = eaddr;
> -                    if (access_type == MMU_DATA_STORE) {
> -                        env->spr[SPR_40x_ESR] = 0x00800000;
> -                    } else {
> -                        env->spr[SPR_40x_ESR] = 0x00000000;
> -                    }
> -                    break;
> -                case POWERPC_MMU_BOOKE206:
> -                    booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> -                    /* fall through */
> -                case POWERPC_MMU_BOOKE:
> -                    cs->exception_index = POWERPC_EXCP_DTLB;
> -                    env->error_code = 0;
> -                    env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> -                    break;
> -                case POWERPC_MMU_REAL:
> -                    cpu_abort(cs, "PowerPC in real mode should never raise "
> +            case POWERPC_MMU_BOOKE206:
> +                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> +                /* fall through */
> +            case POWERPC_MMU_BOOKE:
> +                cs->exception_index = POWERPC_EXCP_DTLB;
> +                env->error_code = 0;
> +                env->spr[SPR_BOOKE_DEAR] = eaddr;
> +                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +                break;
> +            case POWERPC_MMU_REAL:
> +                cpu_abort(cs, "PowerPC in real mode should never raise "
>                                "any MMU exceptions\n");
> -                default:
> -                    cpu_abort(cs, "Unknown or invalid MMU model\n");
> +            default:
> +                cpu_abort(cs, "Unknown or invalid MMU model\n");
> +            }
> +            break;
> +        case -2:
> +            /* Access rights violation */
> +            cs->exception_index = POWERPC_EXCP_DSI;
> +            env->error_code = 0;
> +            if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
> +                env->spr[SPR_40x_DEAR] = eaddr;
> +                if (access_type == MMU_DATA_STORE) {
> +                    env->spr[SPR_40x_ESR] |= 0x00800000;
>                  }
> +            } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> +                       (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> +                env->spr[SPR_BOOKE_DEAR] = eaddr;
> +                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +            } else {
> +                env->spr[SPR_DAR] = eaddr;
> +                if (access_type == MMU_DATA_STORE) {
> +                    env->spr[SPR_DSISR] = 0x0A000000;
> +                } else {
> +                    env->spr[SPR_DSISR] = 0x08000000;
> +                }
> +            }
> +            break;
> +        case -4:
> +            /* Direct store exception */
> +            switch (type) {
> +            case ACCESS_FLOAT:
> +                /* Floating point load/store */
> +                cs->exception_index = POWERPC_EXCP_ALIGN;
> +                env->error_code = POWERPC_EXCP_ALIGN_FP;
> +                env->spr[SPR_DAR] = eaddr;
>                  break;
> -            case -2:
> -                /* Access rights violation */
> +            case ACCESS_RES:
> +                /* lwarx, ldarx or stwcx. */
>                  cs->exception_index = POWERPC_EXCP_DSI;
>                  env->error_code = 0;
> -                if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
> -                    env->spr[SPR_40x_DEAR] = eaddr;
> -                    if (access_type == MMU_DATA_STORE) {
> -                        env->spr[SPR_40x_ESR] |= 0x00800000;
> -                    }
> -                } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                           (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                    env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +                env->spr[SPR_DAR] = eaddr;
> +                if (access_type == MMU_DATA_STORE) {
> +                    env->spr[SPR_DSISR] = 0x06000000;
>                  } else {
> -                    env->spr[SPR_DAR] = eaddr;
> -                    if (access_type == MMU_DATA_STORE) {
> -                        env->spr[SPR_DSISR] = 0x0A000000;
> -                    } else {
> -                        env->spr[SPR_DSISR] = 0x08000000;
> -                    }
> +                    env->spr[SPR_DSISR] = 0x04000000;
>                  }
>                  break;
> -            case -4:
> -                /* Direct store exception */
> -                switch (type) {
> -                case ACCESS_FLOAT:
> -                    /* Floating point load/store */
> -                    cs->exception_index = POWERPC_EXCP_ALIGN;
> -                    env->error_code = POWERPC_EXCP_ALIGN_FP;
> -                    env->spr[SPR_DAR] = eaddr;
> -                    break;
> -                case ACCESS_RES:
> -                    /* lwarx, ldarx or stwcx. */
> -                    cs->exception_index = POWERPC_EXCP_DSI;
> -                    env->error_code = 0;
> -                    env->spr[SPR_DAR] = eaddr;
> -                    if (access_type == MMU_DATA_STORE) {
> -                        env->spr[SPR_DSISR] = 0x06000000;
> -                    } else {
> -                        env->spr[SPR_DSISR] = 0x04000000;
> -                    }
> -                    break;
> -                case ACCESS_EXT:
> -                    /* eciwx or ecowx */
> -                    cs->exception_index = POWERPC_EXCP_DSI;
> -                    env->error_code = 0;
> -                    env->spr[SPR_DAR] = eaddr;
> -                    if (access_type == MMU_DATA_STORE) {
> -                        env->spr[SPR_DSISR] = 0x06100000;
> -                    } else {
> -                        env->spr[SPR_DSISR] = 0x04100000;
> -                    }
> -                    break;
> -                default:
> -                    printf("DSI: invalid exception (%d)\n", ret);
> -                    cs->exception_index = POWERPC_EXCP_PROGRAM;
> -                    env->error_code =
> -                        POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> -                    env->spr[SPR_DAR] = eaddr;
> -                    break;
> +            case ACCESS_EXT:
> +                /* eciwx or ecowx */
> +                cs->exception_index = POWERPC_EXCP_DSI;
> +                env->error_code = 0;
> +                env->spr[SPR_DAR] = eaddr;
> +                if (access_type == MMU_DATA_STORE) {
> +                    env->spr[SPR_DSISR] = 0x06100000;
> +                } else {
> +                    env->spr[SPR_DSISR] = 0x04100000;
>                  }
>                  break;
> +            default:
> +                printf("DSI: invalid exception (%d)\n", ret);
> +                cs->exception_index = POWERPC_EXCP_PROGRAM;
> +                env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> +                env->spr[SPR_DAR] = eaddr;
> +                break;
>              }
> +            break;
>          }
>      }
>      return false;
diff mbox series

Patch

diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 28847c32f2..2487b4deff 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1265,187 +1265,186 @@  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
         *protp = ctx.prot;
         *psizep = TARGET_PAGE_BITS;
         return true;
+    } else if (!guest_visible) {
+        return false;
     }
 
-    if (guest_visible) {
-        log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
-        if (type == ACCESS_CODE) {
-            switch (ret) {
-            case -1:
-                /* No matches in page tables or TLB */
-                switch (env->mmu_model) {
-                case POWERPC_MMU_SOFT_6xx:
-                    cs->exception_index = POWERPC_EXCP_IFTLB;
-                    env->error_code = 1 << 18;
-                    env->spr[SPR_IMISS] = eaddr;
-                    env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
-                    goto tlb_miss;
-                case POWERPC_MMU_SOFT_4xx:
-                    cs->exception_index = POWERPC_EXCP_ITLB;
-                    env->error_code = 0;
-                    env->spr[SPR_40x_DEAR] = eaddr;
-                    env->spr[SPR_40x_ESR] = 0x00000000;
-                    break;
-                case POWERPC_MMU_BOOKE206:
-                    booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
-                    /* fall through */
-                case POWERPC_MMU_BOOKE:
-                    cs->exception_index = POWERPC_EXCP_ITLB;
-                    env->error_code = 0;
-                    env->spr[SPR_BOOKE_DEAR] = eaddr;
-                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
-                    break;
-                case POWERPC_MMU_REAL:
-                    cpu_abort(cs, "PowerPC in real mode should never raise "
-                              "any MMU exceptions\n");
-                default:
-                    cpu_abort(cs, "Unknown or invalid MMU model\n");
-                }
+    log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+    if (type == ACCESS_CODE) {
+        switch (ret) {
+        case -1:
+            /* No matches in page tables or TLB */
+            switch (env->mmu_model) {
+            case POWERPC_MMU_SOFT_6xx:
+                cs->exception_index = POWERPC_EXCP_IFTLB;
+                env->error_code = 1 << 18;
+                env->spr[SPR_IMISS] = eaddr;
+                env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
+                goto tlb_miss;
+            case POWERPC_MMU_SOFT_4xx:
+                cs->exception_index = POWERPC_EXCP_ITLB;
+                env->error_code = 0;
+                env->spr[SPR_40x_DEAR] = eaddr;
+                env->spr[SPR_40x_ESR] = 0x00000000;
                 break;
-            case -2:
-                /* Access rights violation */
-                cs->exception_index = POWERPC_EXCP_ISI;
-                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                    env->error_code = 0;
-                } else {
-                    env->error_code = 0x08000000;
-                }
+            case POWERPC_MMU_BOOKE206:
+                booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
+                /* fall through */
+            case POWERPC_MMU_BOOKE:
+                cs->exception_index = POWERPC_EXCP_ITLB;
+                env->error_code = 0;
+                env->spr[SPR_BOOKE_DEAR] = eaddr;
+                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
                 break;
-            case -3:
-                /* No execute protection violation */
-                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                    env->spr[SPR_BOOKE_ESR] = 0x00000000;
-                    env->error_code = 0;
+            case POWERPC_MMU_REAL:
+                cpu_abort(cs, "PowerPC in real mode should never raise "
+                              "any MMU exceptions\n");
+            default:
+                cpu_abort(cs, "Unknown or invalid MMU model\n");
+            }
+            break;
+        case -2:
+            /* Access rights violation */
+            cs->exception_index = POWERPC_EXCP_ISI;
+            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+                env->error_code = 0;
+            } else {
+                env->error_code = 0x08000000;
+            }
+            break;
+        case -3:
+            /* No execute protection violation */
+            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+                env->spr[SPR_BOOKE_ESR] = 0x00000000;
+                env->error_code = 0;
+            } else {
+                env->error_code = 0x10000000;
+            }
+            cs->exception_index = POWERPC_EXCP_ISI;
+            break;
+        case -4:
+            /* Direct store exception */
+            /* No code fetch is allowed in direct-store areas */
+            cs->exception_index = POWERPC_EXCP_ISI;
+            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+                env->error_code = 0;
+            } else {
+                env->error_code = 0x10000000;
+            }
+            break;
+        }
+    } else {
+        switch (ret) {
+        case -1:
+            /* No matches in page tables or TLB */
+            switch (env->mmu_model) {
+            case POWERPC_MMU_SOFT_6xx:
+                if (access_type == MMU_DATA_STORE) {
+                    cs->exception_index = POWERPC_EXCP_DSTLB;
+                    env->error_code = 1 << 16;
                 } else {
-                    env->error_code = 0x10000000;
+                    cs->exception_index = POWERPC_EXCP_DLTLB;
+                    env->error_code = 0;
                 }
-                cs->exception_index = POWERPC_EXCP_ISI;
+                env->spr[SPR_DMISS] = eaddr;
+                env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
+            tlb_miss:
+                env->error_code |= ctx.key << 19;
+                env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
+                  get_pteg_offset32(cpu, ctx.hash[0]);
+                env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
+                  get_pteg_offset32(cpu, ctx.hash[1]);
                 break;
-            case -4:
-                /* Direct store exception */
-                /* No code fetch is allowed in direct-store areas */
-                cs->exception_index = POWERPC_EXCP_ISI;
-                if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                    (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                    env->error_code = 0;
+            case POWERPC_MMU_SOFT_4xx:
+                cs->exception_index = POWERPC_EXCP_DTLB;
+                env->error_code = 0;
+                env->spr[SPR_40x_DEAR] = eaddr;
+                if (access_type == MMU_DATA_STORE) {
+                    env->spr[SPR_40x_ESR] = 0x00800000;
                 } else {
-                    env->error_code = 0x10000000;
+                    env->spr[SPR_40x_ESR] = 0x00000000;
                 }
                 break;
-            }
-        } else {
-            switch (ret) {
-            case -1:
-                /* No matches in page tables or TLB */
-                switch (env->mmu_model) {
-                case POWERPC_MMU_SOFT_6xx:
-                    if (access_type == MMU_DATA_STORE) {
-                        cs->exception_index = POWERPC_EXCP_DSTLB;
-                        env->error_code = 1 << 16;
-                    } else {
-                        cs->exception_index = POWERPC_EXCP_DLTLB;
-                        env->error_code = 0;
-                    }
-                    env->spr[SPR_DMISS] = eaddr;
-                    env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
-                tlb_miss:
-                    env->error_code |= ctx.key << 19;
-                    env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
-                        get_pteg_offset32(cpu, ctx.hash[0]);
-                    env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
-                        get_pteg_offset32(cpu, ctx.hash[1]);
-                    break;
-                case POWERPC_MMU_SOFT_4xx:
-                    cs->exception_index = POWERPC_EXCP_DTLB;
-                    env->error_code = 0;
-                    env->spr[SPR_40x_DEAR] = eaddr;
-                    if (access_type == MMU_DATA_STORE) {
-                        env->spr[SPR_40x_ESR] = 0x00800000;
-                    } else {
-                        env->spr[SPR_40x_ESR] = 0x00000000;
-                    }
-                    break;
-                case POWERPC_MMU_BOOKE206:
-                    booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
-                    /* fall through */
-                case POWERPC_MMU_BOOKE:
-                    cs->exception_index = POWERPC_EXCP_DTLB;
-                    env->error_code = 0;
-                    env->spr[SPR_BOOKE_DEAR] = eaddr;
-                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
-                    break;
-                case POWERPC_MMU_REAL:
-                    cpu_abort(cs, "PowerPC in real mode should never raise "
+            case POWERPC_MMU_BOOKE206:
+                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+                /* fall through */
+            case POWERPC_MMU_BOOKE:
+                cs->exception_index = POWERPC_EXCP_DTLB;
+                env->error_code = 0;
+                env->spr[SPR_BOOKE_DEAR] = eaddr;
+                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+                break;
+            case POWERPC_MMU_REAL:
+                cpu_abort(cs, "PowerPC in real mode should never raise "
                               "any MMU exceptions\n");
-                default:
-                    cpu_abort(cs, "Unknown or invalid MMU model\n");
+            default:
+                cpu_abort(cs, "Unknown or invalid MMU model\n");
+            }
+            break;
+        case -2:
+            /* Access rights violation */
+            cs->exception_index = POWERPC_EXCP_DSI;
+            env->error_code = 0;
+            if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
+                env->spr[SPR_40x_DEAR] = eaddr;
+                if (access_type == MMU_DATA_STORE) {
+                    env->spr[SPR_40x_ESR] |= 0x00800000;
                 }
+            } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+                       (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+                env->spr[SPR_BOOKE_DEAR] = eaddr;
+                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+            } else {
+                env->spr[SPR_DAR] = eaddr;
+                if (access_type == MMU_DATA_STORE) {
+                    env->spr[SPR_DSISR] = 0x0A000000;
+                } else {
+                    env->spr[SPR_DSISR] = 0x08000000;
+                }
+            }
+            break;
+        case -4:
+            /* Direct store exception */
+            switch (type) {
+            case ACCESS_FLOAT:
+                /* Floating point load/store */
+                cs->exception_index = POWERPC_EXCP_ALIGN;
+                env->error_code = POWERPC_EXCP_ALIGN_FP;
+                env->spr[SPR_DAR] = eaddr;
                 break;
-            case -2:
-                /* Access rights violation */
+            case ACCESS_RES:
+                /* lwarx, ldarx or stwcx. */
                 cs->exception_index = POWERPC_EXCP_DSI;
                 env->error_code = 0;
-                if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
-                    env->spr[SPR_40x_DEAR] = eaddr;
-                    if (access_type == MMU_DATA_STORE) {
-                        env->spr[SPR_40x_ESR] |= 0x00800000;
-                    }
-                } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                           (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                    env->spr[SPR_BOOKE_DEAR] = eaddr;
-                    env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+                env->spr[SPR_DAR] = eaddr;
+                if (access_type == MMU_DATA_STORE) {
+                    env->spr[SPR_DSISR] = 0x06000000;
                 } else {
-                    env->spr[SPR_DAR] = eaddr;
-                    if (access_type == MMU_DATA_STORE) {
-                        env->spr[SPR_DSISR] = 0x0A000000;
-                    } else {
-                        env->spr[SPR_DSISR] = 0x08000000;
-                    }
+                    env->spr[SPR_DSISR] = 0x04000000;
                 }
                 break;
-            case -4:
-                /* Direct store exception */
-                switch (type) {
-                case ACCESS_FLOAT:
-                    /* Floating point load/store */
-                    cs->exception_index = POWERPC_EXCP_ALIGN;
-                    env->error_code = POWERPC_EXCP_ALIGN_FP;
-                    env->spr[SPR_DAR] = eaddr;
-                    break;
-                case ACCESS_RES:
-                    /* lwarx, ldarx or stwcx. */
-                    cs->exception_index = POWERPC_EXCP_DSI;
-                    env->error_code = 0;
-                    env->spr[SPR_DAR] = eaddr;
-                    if (access_type == MMU_DATA_STORE) {
-                        env->spr[SPR_DSISR] = 0x06000000;
-                    } else {
-                        env->spr[SPR_DSISR] = 0x04000000;
-                    }
-                    break;
-                case ACCESS_EXT:
-                    /* eciwx or ecowx */
-                    cs->exception_index = POWERPC_EXCP_DSI;
-                    env->error_code = 0;
-                    env->spr[SPR_DAR] = eaddr;
-                    if (access_type == MMU_DATA_STORE) {
-                        env->spr[SPR_DSISR] = 0x06100000;
-                    } else {
-                        env->spr[SPR_DSISR] = 0x04100000;
-                    }
-                    break;
-                default:
-                    printf("DSI: invalid exception (%d)\n", ret);
-                    cs->exception_index = POWERPC_EXCP_PROGRAM;
-                    env->error_code =
-                        POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
-                    env->spr[SPR_DAR] = eaddr;
-                    break;
+            case ACCESS_EXT:
+                /* eciwx or ecowx */
+                cs->exception_index = POWERPC_EXCP_DSI;
+                env->error_code = 0;
+                env->spr[SPR_DAR] = eaddr;
+                if (access_type == MMU_DATA_STORE) {
+                    env->spr[SPR_DSISR] = 0x06100000;
+                } else {
+                    env->spr[SPR_DSISR] = 0x04100000;
                 }
                 break;
+            default:
+                printf("DSI: invalid exception (%d)\n", ret);
+                cs->exception_index = POWERPC_EXCP_PROGRAM;
+                env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+                env->spr[SPR_DAR] = eaddr;
+                break;
             }
+            break;
         }
     }
     return false;