| Message ID | 20240524-msm-drm-dsc-dsi-video-upstream-4-v4-1-e61c05b403df@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC support to DSI video panel | expand |
On Fri, May 24, 2024 at 09:18:21PM +0800, Jun Nie wrote: > From: Jonathan Marek <jonathan@marek.ca> > > Add necessary DPU timing and control changes for DSC to work with DSI > video mode. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++ > 4 files changed, 26 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 119f3ea50a7c..48cef6e79c70 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) > return (num_dsc > 0) && (num_dsc > intf_count); > } > > -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) > +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) > { > struct msm_drm_private *priv = drm_enc->dev->dev_private; > struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 002e89cc1705..2167c46c1a45 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > */ > unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); > > +/** > + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder > + * This helper function is used by physical encoder to get DSC config > + * used for this encoder. > + * @drm_enc: Pointer to encoder structure > + */ > +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); > + > /** > * dpu_encoder_get_drm_fmt - return DRM fourcc format > * @phys_enc: Pointer to physical encoder structure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ef69c2f408c3..7047b607ca91 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -115,6 +115,19 @@ static void drm_mode_to_intf_timing_params( > timing->h_front_porch = timing->h_front_porch >> 1; > timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; > } > + > + /* > + * for DSI, if compression is enabled, then divide the horizonal active > + * timing parameters by compression ratio. bits of 3 components(R/G/B) > + * is compressed into bits of 1 pixel. > + */ > + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { > + struct drm_dsc_config *dsc = > + dpu_encoder_get_dsc_config(phys_enc->parent); > + timing->width = timing->width * (dsc->bits_per_pixel >> 4) / Here you are truncating fractional part of BPP. Please use drm_dsc_get_bpp_int(), at least it will warn if there is a fractional part. Or, even better, add a helper to calculate width * bpp / 64 / (bpc * 3) and use it here and in dsi_adjust_pclk_for_compression() > + (dsc->bits_per_component * 3); > + timing->xres = timing->width; > + } > } > > static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 225c1c7768ff..2cf1f8c116b5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -168,6 +168,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > > data_width = p->width; > > + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ > + if (p->compression_en && !dp_intf) > + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; > + Separate commit, please > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 119f3ea50a7c..48cef6e79c70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) return (num_dsc > 0) && (num_dsc > intf_count); } -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) { struct msm_drm_private *priv = drm_enc->dev->dev_private; struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 002e89cc1705..2167c46c1a45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( */ unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +/** + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder + * This helper function is used by physical encoder to get DSC config + * used for this encoder. + * @drm_enc: Pointer to encoder structure + */ +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); + /** * dpu_encoder_get_drm_fmt - return DRM fourcc format * @phys_enc: Pointer to physical encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ef69c2f408c3..7047b607ca91 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -115,6 +115,19 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. bits of 3 components(R/G/B) + * is compressed into bits of 1 pixel. + */ + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { + struct drm_dsc_config *dsc = + dpu_encoder_get_dsc_config(phys_enc->parent); + timing->width = timing->width * (dsc->bits_per_pixel >> 4) / + (dsc->bits_per_component * 3); + timing->xres = timing->width; + } } static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 225c1c7768ff..2cf1f8c116b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -168,6 +168,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, data_width = p->width; + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ + if (p->compression_en && !dp_intf) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1;