mbox series

[RISU,v2,00/13] ELF and Sparc64 support

Message ID 20240526193637.459064-1-richard.henderson@linaro.org (mailing list archive)
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Series ELF and Sparc64 support | expand

Message

Richard Henderson May 26, 2024, 7:36 p.m. UTC
Let risu accept elf test files, adjusted from v1.
Adjust risugen to invoke the assembler and linker,
with a cross-compiler prefix if needed.
Add some sparc64 testing which utilizes this.

Changes for v2:
  - Implement VIS2 through VIS4.

There's something odd going on with the Sparc M8 Solaris host where
the values recorded via RISU for some floating-point operations are
incorrectly rounded, but performing the same operations with the
same inputs in a standalone test program produces correct results.

I wonder if there's some unfinished_FPop exception being generated
and the operating system emulation is producing incorrect results.
I'd be much happier if I could test this on Linux...


r~


Richard Henderson (13):
  risu: Allow use of ELF test files
  Build elf test cases instead of raw binaries
  Introduce host_context_t
  risu: Add initial sparc64 support
  risugen: Be explicit about print destinations
  risugen: Add sparc64 support
  contrib/generate_all: Do not rely on ag
  sparc64: Add a few logical insns
  sparc64: Add VIS1 instructions
  sparc64: Add VIS2 and FMAF insns
  sparc64: Add VIS3 instructions
  sparc64: Add IMA instructions
  sparc64: Add VIS4 instructions

 Makefile                   |  22 ++-
 risu.h                     |  16 +-
 risu_reginfo_aarch64.h     |   2 +
 risu_reginfo_arm.h         |   2 +
 risu_reginfo_i386.h        |   2 +
 risu_reginfo_loongarch64.h |   3 +
 risu_reginfo_m68k.h        |   2 +
 risu_reginfo_ppc64.h       |   2 +
 risu_reginfo_s390x.h       |   2 +
 risu_reginfo_sparc64.h     |  36 ++++
 risu.c                     |  59 +++++-
 risu_aarch64.c             |   6 +-
 risu_arm.c                 |   7 +-
 risu_i386.c                |   7 +-
 risu_loongarch64.c         |   6 +-
 risu_m68k.c                |   6 +-
 risu_ppc64.c               |   6 +-
 risu_reginfo_loongarch64.c |   3 +-
 risu_reginfo_sparc64.c     | 186 ++++++++++++++++++
 risu_s390x.c               |   5 +-
 risu_sparc64.c             |  52 +++++
 configure                  |   2 +
 contrib/generate_all.sh    |   4 +-
 risugen                    |  10 +-
 risugen_common.pm          |  68 ++++++-
 risugen_sparc64.pm         | 385 +++++++++++++++++++++++++++++++++++++
 sparc64.risu               | 298 ++++++++++++++++++++++++++++
 test.ld                    |  12 ++
 test_aarch64.s             |   4 +-
 test_arm.s                 |  16 +-
 test_i386.S                |   4 +-
 test_sparc64.s             | 137 +++++++++++++
 32 files changed, 1298 insertions(+), 74 deletions(-)
 create mode 100644 risu_reginfo_sparc64.h
 create mode 100644 risu_reginfo_sparc64.c
 create mode 100644 risu_sparc64.c
 create mode 100644 risugen_sparc64.pm
 create mode 100644 sparc64.risu
 create mode 100644 test.ld
 create mode 100644 test_sparc64.s

Comments

Mark Cave-Ayland May 28, 2024, 8:43 p.m. UTC | #1
On 26/05/2024 20:36, Richard Henderson wrote:

> Let risu accept elf test files, adjusted from v1.
> Adjust risugen to invoke the assembler and linker,
> with a cross-compiler prefix if needed.
> Add some sparc64 testing which utilizes this.
> 
> Changes for v2:
>    - Implement VIS2 through VIS4.
> 
> There's something odd going on with the Sparc M8 Solaris host where
> the values recorded via RISU for some floating-point operations are
> incorrectly rounded, but performing the same operations with the
> same inputs in a standalone test program produces correct results.
> 
> I wonder if there's some unfinished_FPop exception being generated
> and the operating system emulation is producing incorrect results.
> I'd be much happier if I could test this on Linux...
> 
> 
> r~
> 
> 
> Richard Henderson (13):
>    risu: Allow use of ELF test files
>    Build elf test cases instead of raw binaries
>    Introduce host_context_t
>    risu: Add initial sparc64 support
>    risugen: Be explicit about print destinations
>    risugen: Add sparc64 support
>    contrib/generate_all: Do not rely on ag
>    sparc64: Add a few logical insns
>    sparc64: Add VIS1 instructions
>    sparc64: Add VIS2 and FMAF insns
>    sparc64: Add VIS3 instructions
>    sparc64: Add IMA instructions
>    sparc64: Add VIS4 instructions
> 
>   Makefile                   |  22 ++-
>   risu.h                     |  16 +-
>   risu_reginfo_aarch64.h     |   2 +
>   risu_reginfo_arm.h         |   2 +
>   risu_reginfo_i386.h        |   2 +
>   risu_reginfo_loongarch64.h |   3 +
>   risu_reginfo_m68k.h        |   2 +
>   risu_reginfo_ppc64.h       |   2 +
>   risu_reginfo_s390x.h       |   2 +
>   risu_reginfo_sparc64.h     |  36 ++++
>   risu.c                     |  59 +++++-
>   risu_aarch64.c             |   6 +-
>   risu_arm.c                 |   7 +-
>   risu_i386.c                |   7 +-
>   risu_loongarch64.c         |   6 +-
>   risu_m68k.c                |   6 +-
>   risu_ppc64.c               |   6 +-
>   risu_reginfo_loongarch64.c |   3 +-
>   risu_reginfo_sparc64.c     | 186 ++++++++++++++++++
>   risu_s390x.c               |   5 +-
>   risu_sparc64.c             |  52 +++++
>   configure                  |   2 +
>   contrib/generate_all.sh    |   4 +-
>   risugen                    |  10 +-
>   risugen_common.pm          |  68 ++++++-
>   risugen_sparc64.pm         | 385 +++++++++++++++++++++++++++++++++++++
>   sparc64.risu               | 298 ++++++++++++++++++++++++++++
>   test.ld                    |  12 ++
>   test_aarch64.s             |   4 +-
>   test_arm.s                 |  16 +-
>   test_i386.S                |   4 +-
>   test_sparc64.s             | 137 +++++++++++++
>   32 files changed, 1298 insertions(+), 74 deletions(-)
>   create mode 100644 risu_reginfo_sparc64.h
>   create mode 100644 risu_reginfo_sparc64.c
>   create mode 100644 risu_sparc64.c
>   create mode 100644 risugen_sparc64.pm
>   create mode 100644 sparc64.risu
>   create mode 100644 test.ld
>   create mode 100644 test_sparc64.s

Nice! I don't have any experience with RISU so I don't feel too qualified to review 
the series, but obviously there are clear benefits to having SPARC support included :)


ATB,

Mark.