diff mbox series

[v10,15/15] arm64: dts: qcom: sa8775p: add a dedicated memory carveout for TZ

Message ID 20240527-shm-bridge-v10-15-ce7afaa58d3a@linaro.org (mailing list archive)
State Accepted
Headers show
Series firmware: qcom: implement support for and enable SHM bridge | expand

Commit Message

Bartosz Golaszewski May 27, 2024, 12:55 p.m. UTC
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

Add a 20MB reserved memory region for use by SCM calls.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Konrad Dybcio May 29, 2024, 2:26 p.m. UTC | #1
On 27.05.2024 2:55 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Add a 20MB reserved memory region for use by SCM calls.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 31de73594839..c183527452d7 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -208,6 +208,7 @@ core3 {
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-sa8775p", "qcom,scm";
> +			memory-region = <&tz_ffi_mem>;
>  		};
>  	};
>  
> @@ -418,6 +419,12 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
>  			no-map;
>  		};
>  
> +		tz_ffi_mem: tz-ffi@91c00000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x91c00000 0x0 0x1400000>;

How does that size relate to 

+	pool_config.max_size = SZ_256K;

in patch 3?

Konrad
Bartosz Golaszewski May 29, 2024, 2:39 p.m. UTC | #2
On Wed, May 29, 2024 at 4:26 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 27.05.2024 2:55 PM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >
> > Add a 20MB reserved memory region for use by SCM calls.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > index 31de73594839..c183527452d7 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > @@ -208,6 +208,7 @@ core3 {
> >       firmware {
> >               scm {
> >                       compatible = "qcom,scm-sa8775p", "qcom,scm";
> > +                     memory-region = <&tz_ffi_mem>;
> >               };
> >       };
> >
> > @@ -418,6 +419,12 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
> >                       no-map;
> >               };
> >
> > +             tz_ffi_mem: tz-ffi@91c00000 {
> > +                     compatible = "shared-dma-pool";
> > +                     reg = <0x0 0x91c00000 0x0 0x1400000>;
>
> How does that size relate to
>
> +       pool_config.max_size = SZ_256K;
>
> in patch 3?
>
> Konrad

Short answer: it doesn't.

Slightly less short answer: this is the limit of *this* specific TZMem
pool which in turn gets its memory from the shared DMA pool. We can
have multiple TZMem pools and they all share this DMA pool.

Bartosz
Konrad Dybcio May 31, 2024, 12:40 p.m. UTC | #3
On 29.05.2024 4:39 PM, Bartosz Golaszewski wrote:
> On Wed, May 29, 2024 at 4:26 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 27.05.2024 2:55 PM, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>>
>>> Add a 20MB reserved memory region for use by SCM calls.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++
>>>  1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> index 31de73594839..c183527452d7 100644
>>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> @@ -208,6 +208,7 @@ core3 {
>>>       firmware {
>>>               scm {
>>>                       compatible = "qcom,scm-sa8775p", "qcom,scm";
>>> +                     memory-region = <&tz_ffi_mem>;
>>>               };
>>>       };
>>>
>>> @@ -418,6 +419,12 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
>>>                       no-map;
>>>               };
>>>
>>> +             tz_ffi_mem: tz-ffi@91c00000 {
>>> +                     compatible = "shared-dma-pool";
>>> +                     reg = <0x0 0x91c00000 0x0 0x1400000>;
>>
>> How does that size relate to
>>
>> +       pool_config.max_size = SZ_256K;
>>
>> in patch 3?
>>
>> Konrad
> 
> Short answer: it doesn't.
> 
> Slightly less short answer: this is the limit of *this* specific TZMem
> pool which in turn gets its memory from the shared DMA pool. We can
> have multiple TZMem pools and they all share this DMA pool.

OK makes sense, thanks

Konrad
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 31de73594839..c183527452d7 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -208,6 +208,7 @@  core3 {
 	firmware {
 		scm {
 			compatible = "qcom,scm-sa8775p", "qcom,scm";
+			memory-region = <&tz_ffi_mem>;
 		};
 	};
 
@@ -418,6 +419,12 @@  cdt_data_backup_mem: cdt-data-backup@91ba0000 {
 			no-map;
 		};
 
+		tz_ffi_mem: tz-ffi@91c00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x91c00000 0x0 0x1400000>;
+			no-map;
+		};
+
 		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
 			reg = <0x0 0x93b00000 0x0 0xf00000>;
 			no-map;