diff mbox series

[3/6] host/i386: assume presence of CMOV

Message ID 20240531091457.42200-4-pbonzini@redhat.com (mailing list archive)
State New, archived
Headers show
Series host/i386: require x86-64-v2 ISA | expand

Commit Message

Paolo Bonzini May 31, 2024, 9:14 a.m. UTC 
QEMU now requires an x86-64-v2 host, which always has CMOV.
Use it freely in TCG generated code.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 host/include/i386/host/cpuinfo.h |  1 -
 util/cpuinfo-i386.c              |  1 -
 tcg/i386/tcg-target.c.inc        | 15 +--------------
 3 files changed, 1 insertion(+), 16 deletions(-)

Comments

Zhao Liu June 2, 2024, 9:29 a.m. UTC | #1 
On Fri, May 31, 2024 at 11:14:54AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:54 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 3/6] host/i386: assume presence of CMOV
> X-Mailer: git-send-email 2.45.1
> 
> QEMU now requires an x86-64-v2 host, which always has CMOV.
> Use it freely in TCG generated code.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  host/include/i386/host/cpuinfo.h |  1 -
>  util/cpuinfo-i386.c              |  1 -
>  tcg/i386/tcg-target.c.inc        | 15 +--------------
>  3 files changed, 1 insertion(+), 16 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
diff mbox series

Patch

diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h
index 9386c749881..81771733eaa 100644
--- a/host/include/i386/host/cpuinfo.h
+++ b/host/include/i386/host/cpuinfo.h
@@ -9,7 +9,6 @@ 
 /* Digested version of <cpuid.h> */
 
 #define CPUINFO_ALWAYS          (1u << 0)  /* so cpuinfo is nonzero */
-#define CPUINFO_CMOV            (1u << 1)
 #define CPUINFO_MOVBE           (1u << 2)
 #define CPUINFO_LZCNT           (1u << 3)
 #define CPUINFO_POPCNT          (1u << 4)
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index 18ab747a6d2..90f92a42dc8 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -34,7 +34,6 @@  unsigned __attribute__((constructor)) cpuinfo_init(void)
     if (max >= 1) {
         __cpuid(1, a, b, c, d);
 
-        info |= (d & bit_CMOV ? CPUINFO_CMOV : 0);
         info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 59235b4f387..9a54ef7f8db 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -157,12 +157,6 @@  static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
 #define SOFTMMU_RESERVE_REGS \
     (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
 
-/* For 64-bit, we always know that CMOV is available.  */
-#if TCG_TARGET_REG_BITS == 64
-# define have_cmov      true
-#else
-# define have_cmov      (cpuinfo & CPUINFO_CMOV)
-#endif
 #define have_bmi2       (cpuinfo & CPUINFO_BMI2)
 #define have_lzcnt      (cpuinfo & CPUINFO_LZCNT)
 
@@ -1815,14 +1809,7 @@  static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
 static void tcg_out_cmov(TCGContext *s, int jcc, int rexw,
                          TCGReg dest, TCGReg v1)
 {
-    if (have_cmov) {
-        tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
-    } else {
-        TCGLabel *over = gen_new_label();
-        tcg_out_jxx(s, jcc ^ 1, over, 1);
-        tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
-        tcg_out_label(s, over);
-    }
+    tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
 }
 
 static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond,