diff mbox series

arm64: dts: qcom: sa8775p: Correct IRQ number of EL2 non-secure physical timer

Message ID 20240604085929.49227-1-quic_congzhan@quicinc.com (mailing list archive)
State Accepted
Commit 41fca5930afb36453cc90d4002841edd9990d0ad
Headers show
Series arm64: dts: qcom: sa8775p: Correct IRQ number of EL2 non-secure physical timer | expand

Commit Message

Cong Zhang June 4, 2024, 8:59 a.m. UTC
The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ
number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number
of EL2 non-secure physical timer should be 10 (26 - 16).

Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
---
ARM documentation for reference:
https://developer.arm.com/documentation/102379/0103/The-processor-timers/Summary-table

---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Krzysztof Kozlowski June 4, 2024, 9:08 a.m. UTC | #1
On 04/06/2024 10:59, Cong Zhang wrote:
> The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ
> number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number
> of EL2 non-secure physical timer should be 10 (26 - 16).
> 
> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")

Please add Cc stable. See stable kernel guidelines.

> Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Konrad Dybcio June 4, 2024, 11:57 a.m. UTC | #2
On 6/4/24 10:59, Cong Zhang wrote:
> The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ
> number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number
> of EL2 non-secure physical timer should be 10 (26 - 16).
> 
> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
> Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
> ---

Seems to match other qcom platforms of the timeframe too..

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Bjorn Andersson June 4, 2024, 8:11 p.m. UTC | #3
On Tue, 04 Jun 2024 16:59:29 +0800, Cong Zhang wrote:
> The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ
> number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number
> of EL2 non-secure physical timer should be 10 (26 - 16).
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sa8775p: Correct IRQ number of EL2 non-secure physical timer
      commit: 41fca5930afb36453cc90d4002841edd9990d0ad

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 89496728d840..efd588fa2abb 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4566,7 +4566,7 @@  arch_timer: timer {
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	pcie0: pcie@1c00000 {