diff mbox series

[v2,08/37] target/sparc: Use gvec for VIS1 parallel add/sub

Message ID 20240526194254.459395-9-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series target/sparc: Implement VIS4 | expand

Commit Message

Richard Henderson May 26, 2024, 7:42 p.m. UTC 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

Comments

Philippe Mathieu-Daudé June 4, 2024, 1:18 p.m. UTC | #1 
On 26/5/24 21:42, Richard Henderson wrote:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sparc/translate.c | 18 ++++++++++++++----
>   1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index 362e88de18..8731e4f8bb 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -4664,6 +4664,20 @@ static bool do_dfd(DisasContext *dc, arg_r_r_r *a,
>   
>   TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16)
>   
> +static bool do_gvec_ddd(DisasContext *dc, arg_r_r_r *a, MemOp vece,
> +                        void (*func)(unsigned, uint32_t, uint32_t,
> +                                     uint32_t, uint32_t, uint32_t))
> +{

I missed the FPU check I guess:

     if (gen_trap_ifnofpu(dc)) {
         return true;
     }

> +    func(vece, gen_offset_fpr_D(a->rd), gen_offset_fpr_D(a->rs1),
> +         gen_offset_fpr_D(a->rs2), 8, 8);
> +    return advance_pc(dc);
> +}
diff mbox series

Patch

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 362e88de18..8731e4f8bb 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4664,6 +4664,20 @@  static bool do_dfd(DisasContext *dc, arg_r_r_r *a,
 
 TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16)
 
+static bool do_gvec_ddd(DisasContext *dc, arg_r_r_r *a, MemOp vece,
+                        void (*func)(unsigned, uint32_t, uint32_t,
+                                     uint32_t, uint32_t, uint32_t))
+{
+    func(vece, gen_offset_fpr_D(a->rd), gen_offset_fpr_D(a->rs1),
+         gen_offset_fpr_D(a->rs2), 8, 8);
+    return advance_pc(dc);
+}
+
+TRANS(FPADD16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_add)
+TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_add)
+TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub)
+TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub)
+
 static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
 {
@@ -4684,10 +4698,6 @@  static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
 TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16)
 TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16)
 
-TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64)
-TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64)
-TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64)
-TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64)
 TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64)
 TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64)
 TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64)