| Message ID | 20240605172253.356302-1-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 6/5/24 12:22, Richard Henderson wrote: > The following changes since commit d16cab541ab9217977e2a39abf3d79f914146741: > > Merge tag 'hw-misc-accel-20240604' ofhttps://github.com/philmd/qemu into staging (2024-06-04 14:53:05 -0500) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-sp-20240605 > > for you to fetch changes up to b12b72274320ce3ee516d963efd48766163cb240: > > target/sparc: Enable VIS4 feature bit (2024-06-05 09:11:17 -0700) > > ---------------------------------------------------------------- > target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions > linux-user: Add ioctl for BLKBSZSET Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
The following changes since commit d16cab541ab9217977e2a39abf3d79f914146741: Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into staging (2024-06-04 14:53:05 -0500) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-sp-20240605 for you to fetch changes up to b12b72274320ce3ee516d963efd48766163cb240: target/sparc: Enable VIS4 feature bit (2024-06-05 09:11:17 -0700) ---------------------------------------------------------------- target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions linux-user: Add ioctl for BLKBSZSET ---------------------------------------------------------------- Michael Vogt (1): linux-user: Add ioctl for BLKBSZSET Richard Henderson (37): target/sparc: Fix ARRAY8 target/sparc: Rewrite gen_edge target/sparc: Fix do_dc target/sparc: Fix helper_fmul8ulx16 target/sparc: Perform DFPREG/QFPREG in decodetree target/sparc: Remove gen_dest_fpr_D target/sparc: Remove cpu_fpr[] target/sparc: Use gvec for VIS1 parallel add/sub target/sparc: Implement FMAf extension target/sparc: Add feature bits for VIS 3 target/sparc: Implement ADDXC, ADDXCcc target/sparc: Implement CMASK instructions target/sparc: Implement FCHKSM16 target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL target/sparc: Implement FLCMP target/sparc: Implement FMEAN16 target/sparc: Implement FPADD64, FPSUB64 target/sparc: Implement FPADDS, FPSUBS target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 target/sparc: Implement FSLL, FSRL, FSRA, FSLAS target/sparc: Implement LDXEFSR target/sparc: Implement LZCNT target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd target/sparc: Implement PDISTN target/sparc: Implement UMULXHI target/sparc: Implement XMULX target/sparc: Enable VIS3 feature bit target/sparc: Implement IMA extension target/sparc: Add feature bit for VIS4 target/sparc: Implement FALIGNDATAi target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS target/sparc: Implement VIS4 comparisons target/sparc: Implement FPMIN, FPMAX target/sparc: Implement SUBXC, SUBXCcc target/sparc: Implement MWAIT target/sparc: Implement monitor ASIs target/sparc: Enable VIS4 feature bit linux-user/ioctls.h | 1 + target/sparc/asi.h | 4 + target/sparc/helper.h | 27 +- target/sparc/cpu-feature.h.inc | 4 + target/sparc/insns.decode | 338 +++++++++++---- linux-user/elfload.c | 3 + target/sparc/cpu.c | 12 + target/sparc/fop_helper.c | 136 ++++++ target/sparc/ldst_helper.c | 4 + target/sparc/translate.c | 942 +++++++++++++++++++++++++++++++++-------- target/sparc/vis_helper.c | 392 ++++++++++++++--- fpu/softfloat-specialize.c.inc | 31 ++ 12 files changed, 1563 insertions(+), 331 deletions(-)