| Message ID | 8453205c9619bb8453bf4904d0c5bb868f614fc4.1717514638.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: finish the job of removing implicit dev_priv | expand |
On Tue, Jun 04, 2024 at 06:25:34PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the PFIT_PGM_RATIOS register macro. > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_overlay.c | 5 +++-- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 3 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 49672694293f..1e2ddae5ba94 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1864,7 +1864,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) > intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); > assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); > > - intel_de_write(dev_priv, PFIT_PGM_RATIOS, > + intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv), > crtc_state->gmch_pfit.pgm_ratios); > intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), > crtc_state->gmch_pfit.control); > @@ -2990,7 +2990,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) > > crtc_state->gmch_pfit.control = tmp; > crtc_state->gmch_pfit.pgm_ratios = > - intel_de_read(dev_priv, PFIT_PGM_RATIOS); > + intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); > } > > static enum intel_output_format > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c > index e41881f08d1f..117120ce5a1d 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -943,7 +943,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) > * line with the intel documentation for the i965 > */ > if (DISPLAY_VER(dev_priv) >= 4) { > - u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); > + u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); > > /* on i965 use the PGM reg to read out the autoscaler values */ > ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); > @@ -953,7 +953,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) > if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) > tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); > else > - tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); > + tmp = intel_de_read(dev_priv, > + PFIT_PGM_RATIOS(dev_priv)); > > ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b0dbe6113bbc..094e693c40bf 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1609,7 +1609,7 @@ > #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ > #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ > > -#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) > +#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) > #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ > #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) > #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ > -- > 2.39.2 >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 49672694293f..1e2ddae5ba94 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1864,7 +1864,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); - intel_de_write(dev_priv, PFIT_PGM_RATIOS, + intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv), crtc_state->gmch_pfit.pgm_ratios); intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), crtc_state->gmch_pfit.control); @@ -2990,7 +2990,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) crtc_state->gmch_pfit.control = tmp; crtc_state->gmch_pfit.pgm_ratios = - intel_de_read(dev_priv, PFIT_PGM_RATIOS); + intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); } static enum intel_output_format diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index e41881f08d1f..117120ce5a1d 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -943,7 +943,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) * line with the intel documentation for the i965 */ if (DISPLAY_VER(dev_priv) >= 4) { - u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); + u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); /* on i965 use the PGM reg to read out the autoscaler values */ ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); @@ -953,7 +953,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); else - tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); + tmp = intel_de_read(dev_priv, + PFIT_PGM_RATIOS(dev_priv)); ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b0dbe6113bbc..094e693c40bf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1609,7 +1609,7 @@ #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ -#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) +#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_PGM_RATIOS register macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_overlay.c | 5 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-)