| Message ID | 20240606133628.3330423-5-luca.fancellu@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Armv8-R AArch64 support | expand |
On Thu, 6 Jun 2024 14:36:25 +0100 Luca Fancellu <luca.fancellu@arm.com> wrote: Hi, > This is a preparation for allowing boot-wrapper configuring the gicv3 > with EL2. > > When supporting boot at EL2 for Armv8-R, the architecture does not > define ICC_CTLR_EL2. > See [https://developer.arm.com/documentation/ihi0069/latest/]. > > As the caller, gic_secure_init expects the ICC_CTLR to be written, > we change the function into gic_init_icc_ctlr(). In the GIC spec, > the r/w bits in this register ([6:0]) either affect EL3 IRQ routing > (not applicable since no EL3), non-secure IRQ handling (not applicable > since only secure state in Armv8-R aarch64), or are aliased to > ICC_CTLR_EL1 bits. > So, based on this, the new gic_init_icc_ctlr() would be: > When currentEL is EL3, init ICC_CTLR_EL3 as before. > When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Looks alright, for the purpose of initialising the registers with zero, the two registers behave the same. > Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre > --- > arch/aarch32/include/asm/gic-v3.h | 7 +++++++ > arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++--- > common/gic-v3.c | 2 +- > 3 files changed, 25 insertions(+), 4 deletions(-) > > diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h > index b28136af7fe1..fdfbef859517 100644 > --- a/arch/aarch32/include/asm/gic-v3.h > +++ b/arch/aarch32/include/asm/gic-v3.h > @@ -11,6 +11,8 @@ > > #include <asm/cpu.h> > > +#define ICC_CTLR_RESET (0UL) > + > static inline void gic_write_icc_sre(uint32_t val) > { > mcr(ICC_SRE, val); > @@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) > mcr(ICC_CTLR, val); > } > > +static inline void gic_init_icc_ctlr() > +{ > + gic_write_icc_ctlr(ICC_CTLR_RESET); > +} > + > #endif > diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h > index 24474807c6fe..aca7ab140ed5 100644 > --- a/arch/aarch64/include/asm/gic-v3.h > +++ b/arch/aarch64/include/asm/gic-v3.h > @@ -11,14 +11,28 @@ > > #include <asm/cpu.h> > > +#define ICC_CTLR_EL3_RESET (0UL) > +#define ICC_CTLR_EL1_RESET (0UL) > + > +static inline uint32_t current_el(void) > +{ > + return mrs(CurrentEL); > +} > + > static inline void gic_write_icc_sre(uint32_t val) > { > - msr(ICC_SRE_EL3, val); > + if (current_el() == CURRENTEL_EL3) > + msr(ICC_SRE_EL3, val); > + else > + msr(ICC_SRE_EL2, val); > } > > -static inline void gic_write_icc_ctlr(uint32_t val) > +static inline void gic_init_icc_ctlr() > { > - msr(ICC_CTLR_EL3, val); > + if (current_el() == CURRENTEL_EL3) > + msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET); > + else > + msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET); > } > > #endif > diff --git a/common/gic-v3.c b/common/gic-v3.c > index 6207007959bd..a0fe5642257e 100644 > --- a/common/gic-v3.c > +++ b/common/gic-v3.c > @@ -117,6 +117,6 @@ void gic_secure_init(void) > gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE); > isb(); > > - gic_write_icc_ctlr(0); > + gic_init_icc_ctlr(); > isb(); > }
diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index b28136af7fe1..fdfbef859517 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -11,6 +11,8 @@ #include <asm/cpu.h> +#define ICC_CTLR_RESET (0UL) + static inline void gic_write_icc_sre(uint32_t val) { mcr(ICC_SRE, val); @@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) mcr(ICC_CTLR, val); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index 24474807c6fe..aca7ab140ed5 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -11,14 +11,28 @@ #include <asm/cpu.h> +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + return mrs(CurrentEL); +} + static inline void gic_write_icc_sre(uint32_t val) { - msr(ICC_SRE_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_SRE_EL3, val); + else + msr(ICC_SRE_EL2, val); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_init_icc_ctlr() { - msr(ICC_CTLR_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET); + else + msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET); } #endif diff --git a/common/gic-v3.c b/common/gic-v3.c index 6207007959bd..a0fe5642257e 100644 --- a/common/gic-v3.c +++ b/common/gic-v3.c @@ -117,6 +117,6 @@ void gic_secure_init(void) gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); }
This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. When supporting boot at EL2 for Armv8-R, the architecture does not define ICC_CTLR_EL2. See [https://developer.arm.com/documentation/ihi0069/latest/]. As the caller, gic_secure_init expects the ICC_CTLR to be written, we change the function into gic_init_icc_ctlr(). In the GIC spec, the r/w bits in this register ([6:0]) either affect EL3 IRQ routing (not applicable since no EL3), non-secure IRQ handling (not applicable since only secure state in Armv8-R aarch64), or are aliased to ICC_CTLR_EL1 bits. So, based on this, the new gic_init_icc_ctlr() would be: When currentEL is EL3, init ICC_CTLR_EL3 as before. When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> --- arch/aarch32/include/asm/gic-v3.h | 7 +++++++ arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++--- common/gic-v3.c | 2 +- 3 files changed, 25 insertions(+), 4 deletions(-)