| Message ID | 20240605-configure_ethernet_host_dma_width-v2-1-4cc34edfa388@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0579f27249047006a818e463ee66a6c314d04cea |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net,v2] net: stmmac: dwmac-qcom-ethqos: Configure host DMA width | expand |
On Wed, Jun 05, 2024 at 11:57:18AM -0700, Sagar Cheluvegowda wrote: > Commit 070246e4674b ("net: stmmac: Fix for mismatched host/device DMA > address width") added support in the stmmac driver for platform drivers > to indicate the host DMA width, but left it up to authors of the > specific platforms to indicate if their width differed from the addr64 > register read from the MAC itself. > > Qualcomm's EMAC4 integration supports only up to 36 bit width (as > opposed to the addr64 register indicating 40 bit width). Let's indicate > that in the platform driver to avoid a scenario where the driver will > allocate descriptors of size that is supported by the CPU which in our > case is 36 bit, but as the addr64 register is still capable of 40 bits > the device will use two descriptors as one address. > > Fixes: 8c4d92e82d50 ("net: stmmac: dwmac-qcom-ethqos: add support for emac4 on sa8775p platforms") > Signed-off-by: Sagar Cheluvegowda <quic_scheluve@quicinc.com> > --- > Changes in v2: > Fix commit message to include a commit body > Replace the proper fixes tag > Remove the change-Id > - Link to v1: https://lore.kernel.org/r/20240529-configure_ethernet_host_dma_width-v1-1-3f2707851adf@quicinc.com Thanks, this change looks good to me - the usage of dma_addr_width is in line with my understanding of how it is intended to be used. And, AFAICS, the changes in v2 address the review of v1. Reviewed-by: Simon Horman <horms@kernel.org> ...
On Wed, Jun 05, 2024 at 11:57:18AM GMT, Sagar Cheluvegowda wrote: > Commit 070246e4674b ("net: stmmac: Fix for mismatched host/device DMA > address width") added support in the stmmac driver for platform drivers > to indicate the host DMA width, but left it up to authors of the > specific platforms to indicate if their width differed from the addr64 > register read from the MAC itself. > > Qualcomm's EMAC4 integration supports only up to 36 bit width (as > opposed to the addr64 register indicating 40 bit width). Let's indicate > that in the platform driver to avoid a scenario where the driver will > allocate descriptors of size that is supported by the CPU which in our > case is 36 bit, but as the addr64 register is still capable of 40 bits > the device will use two descriptors as one address. > > Fixes: 8c4d92e82d50 ("net: stmmac: dwmac-qcom-ethqos: add support for emac4 on sa8775p platforms") > Signed-off-by: Sagar Cheluvegowda <quic_scheluve@quicinc.com> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> > --- > Changes in v2: > Fix commit message to include a commit body > Replace the proper fixes tag > Remove the change-Id > - Link to v1: https://lore.kernel.org/r/20240529-configure_ethernet_host_dma_width-v1-1-3f2707851adf@quicinc.com > --- > drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > index e254b21fdb59..65d7370b47d5 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > @@ -93,6 +93,7 @@ struct ethqos_emac_driver_data { > bool has_emac_ge_3; > const char *link_clk_name; > bool has_integrated_pcs; > + u32 dma_addr_width; > struct dwmac4_addrs dwmac4_addrs; > }; > > @@ -276,6 +277,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { > .has_emac_ge_3 = true, > .link_clk_name = "phyaux", > .has_integrated_pcs = true, > + .dma_addr_width = 36, > .dwmac4_addrs = { > .dma_chan = 0x00008100, > .dma_chan_offset = 0x1000, > @@ -845,6 +847,8 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; > if (data->has_integrated_pcs) > plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; > + if (data->dma_addr_width) > + plat_dat->host_dma_width = data->dma_addr_width; > > if (ethqos->serdes_phy) { > plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; > > --- > base-commit: 1b10b390d945a19747d75b34a6e01035ac7b9155 > change-id: 20240515-configure_ethernet_host_dma_width-c619d552992d > > Best regards, > -- > Sagar Cheluvegowda <quic_scheluve@quicinc.com> >
Hello: This patch was applied to netdev/net.git (main) by David S. Miller <davem@davemloft.net>: On Wed, 5 Jun 2024 11:57:18 -0700 you wrote: > Commit 070246e4674b ("net: stmmac: Fix for mismatched host/device DMA > address width") added support in the stmmac driver for platform drivers > to indicate the host DMA width, but left it up to authors of the > specific platforms to indicate if their width differed from the addr64 > register read from the MAC itself. > > Qualcomm's EMAC4 integration supports only up to 36 bit width (as > opposed to the addr64 register indicating 40 bit width). Let's indicate > that in the platform driver to avoid a scenario where the driver will > allocate descriptors of size that is supported by the CPU which in our > case is 36 bit, but as the addr64 register is still capable of 40 bits > the device will use two descriptors as one address. > > [...] Here is the summary with links: - [net,v2] net: stmmac: dwmac-qcom-ethqos: Configure host DMA width https://git.kernel.org/netdev/net/c/0579f2724904 You are awesome, thank you!
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index e254b21fdb59..65d7370b47d5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -93,6 +93,7 @@ struct ethqos_emac_driver_data { bool has_emac_ge_3; const char *link_clk_name; bool has_integrated_pcs; + u32 dma_addr_width; struct dwmac4_addrs dwmac4_addrs; }; @@ -276,6 +277,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .has_emac_ge_3 = true, .link_clk_name = "phyaux", .has_integrated_pcs = true, + .dma_addr_width = 36, .dwmac4_addrs = { .dma_chan = 0x00008100, .dma_chan_offset = 0x1000, @@ -845,6 +847,8 @@ static int qcom_ethqos_probe(struct platform_device *pdev) plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; if (data->has_integrated_pcs) plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; + if (data->dma_addr_width) + plat_dat->host_dma_width = data->dma_addr_width; if (ethqos->serdes_phy) { plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
Commit 070246e4674b ("net: stmmac: Fix for mismatched host/device DMA address width") added support in the stmmac driver for platform drivers to indicate the host DMA width, but left it up to authors of the specific platforms to indicate if their width differed from the addr64 register read from the MAC itself. Qualcomm's EMAC4 integration supports only up to 36 bit width (as opposed to the addr64 register indicating 40 bit width). Let's indicate that in the platform driver to avoid a scenario where the driver will allocate descriptors of size that is supported by the CPU which in our case is 36 bit, but as the addr64 register is still capable of 40 bits the device will use two descriptors as one address. Fixes: 8c4d92e82d50 ("net: stmmac: dwmac-qcom-ethqos: add support for emac4 on sa8775p platforms") Signed-off-by: Sagar Cheluvegowda <quic_scheluve@quicinc.com> --- Changes in v2: Fix commit message to include a commit body Replace the proper fixes tag Remove the change-Id - Link to v1: https://lore.kernel.org/r/20240529-configure_ethernet_host_dma_width-v1-1-3f2707851adf@quicinc.com --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: 1b10b390d945a19747d75b34a6e01035ac7b9155 change-id: 20240515-configure_ethernet_host_dma_width-c619d552992d Best regards,